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FEX-Emu--FEX/FEXCore/Source/Interface/Core/JIT
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Alyssa Rosenzweig 6927c7577a RegisterAllocationPass: delete trivial instructions 
lots of instructions only exist for RA, so RA can garbage collect them before
post-RA passes (including the JIT) deals with them. this simplifies our life
now, and makes post-RA passes a LOT simpler for little cost.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2025-05-26 15:52:23 -04:00
..
ALUOps.cpp
JIT: make almost all the DEF_OPs common
2025-05-19 13:42:59 -04:00
Arm64Relocations.cpp
Drop use of assume-asserting logging macros
2025-01-21 12:01:33 +01:00
AtomicOps.cpp
JIT: make almost all the DEF_OPs common
2025-05-19 13:42:59 -04:00
BranchOps.cpp
JIT: make almost all the DEF_OPs common
2025-05-19 13:42:59 -04:00
ConversionOps.cpp
JIT: make almost all the DEF_OPs common
2025-05-19 13:42:59 -04:00
EncryptionOps.cpp
JIT: make almost all the DEF_OPs common
2025-05-19 13:42:59 -04:00
JIT.cpp
IR: drop RegisterAllocationData
2025-05-19 13:42:59 -04:00
JITClass.h
IR: drop RegisterAllocationData
2025-05-19 13:42:59 -04:00
MemoryOps.cpp
RegisterAllocationPass: delete trivial instructions
2025-05-26 15:52:23 -04:00
MiscOps.cpp
RegisterAllocationPass: delete trivial instructions
2025-05-26 15:52:23 -04:00
MoveOps.cpp
RegisterAllocationPass: delete trivial instructions
2025-05-26 15:52:23 -04:00
VectorOps.cpp
JIT: make almost all the DEF_OPs common
2025-05-19 13:42:59 -04:00