Alyssa Rosenzweig 3b2100307e OpcodeDispatcher: allow garbage on more shifts ...

we're masking anyway

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2024-05-20 10:33:15 -04:00

..

Config

Arm64: Adds another TSO hack to disable half-barrier TSO

2024-04-24 13:09:00 -07:00

Context

IR: drop IRParser

2024-05-08 14:16:54 -04:00

Core

OpcodeDispatcher: allow garbage on more shifts

2024-05-20 10:33:15 -04:00

GDBJIT

Whole-tree reformat

2024-04-12 16:26:02 +02:00

HLE/Thunks

IR: specify registers, not offsets for SRA

2024-05-08 14:01:42 -04:00

IR

ConstProp: Bandage fix for instcountci

2024-05-18 18:06:25 -07:00