mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-07 00:00:17 +02:00
LC
70eafc4f6f
Makes them internally linked, and also lets them be caught by the compiler when they're unused.
507 lines
18 KiB
C++
507 lines
18 KiB
C++
// SPDX-License-Identifier: MIT
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#include "Common/cpp-optparse/OptionParser.h"
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#include "Common/Config.h"
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#include "Common/FEXServerClient.h"
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#include "Common/HostFeatures.h"
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#include "git_version.h"
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#include <FEXCore/Config/Config.h>
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#include <FEXCore/Utils/PrctlUtils.h>
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#include <FEXCore/fextl/fmt.h>
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#include <FEXCore/fextl/string.h>
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#include <FEXHeaderUtils/Filesystem.h>
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#include <cstdio>
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#include <filesystem>
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#include <string>
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#include <sys/prctl.h>
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#include <signal.h>
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#include <ucontext.h>
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#ifdef ARCHITECTURE_arm64
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namespace {
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struct TSOEmulationFacts {
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bool LSE {}, LSE2 {};
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bool HardwareTSO {};
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bool LRCPC1 {}, LRCPC2 {}, LRCPC3 {};
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};
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bool CheckForHardwareTSO() {
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// Check to see if this is supported.
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auto Result = prctl(PR_GET_MEM_MODEL, 0, 0, 0, 0);
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if (Result == -1) {
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// Unsupported, early exit.
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return false;
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}
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if (Result == PR_SET_MEM_MODEL_DEFAULT) {
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// Try to set the TSO mode if we are currently default.
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Result = prctl(PR_SET_MEM_MODEL, PR_SET_MEM_MODEL_TSO, 0, 0, 0);
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if (Result == 0) {
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Result = prctl(PR_SET_MEM_MODEL, PR_SET_MEM_MODEL_DEFAULT, 0, 0, 0);
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return true;
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}
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}
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return false;
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}
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enum ISAR0_FIELDS {
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LSE = 20,
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};
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enum ISAR1_FIELDS {
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LRCPC = 20,
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};
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enum MMFR2_FIELDS {
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AT = 32,
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};
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constexpr static uint32_t IDFIELDMASK = 0b1111;
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uint64_t GetISAR0() {
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uint64_t Result {};
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asm("mrs %0, ID_AA64ISAR0_EL1;" : "=r"(Result));
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return Result;
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}
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uint64_t GetISAR1() {
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uint64_t Result {};
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asm("mrs %0, ID_AA64ISAR1_EL1;" : "=r"(Result));
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return Result;
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}
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uint64_t GetMMFR2() {
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uint64_t Result {};
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asm("mrs %0, ID_AA64MMFR2_EL1;" : "=r"(Result));
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return Result;
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}
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TSOEmulationFacts GetTSOEmulationFacts() {
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const auto ISAR0 = GetISAR0();
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const auto ISAR1 = GetISAR1();
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const auto MMFR2 = GetMMFR2();
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return {
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.LSE = ((ISAR0 >> ISAR0_FIELDS::LSE) & IDFIELDMASK) >= 0b0010,
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.LSE2 = ((MMFR2 >> MMFR2_FIELDS::AT) & IDFIELDMASK) >= 0b0001,
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.HardwareTSO = CheckForHardwareTSO(),
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.LRCPC1 = ((ISAR1 >> ISAR1_FIELDS::LRCPC) & IDFIELDMASK) >= 0b0001,
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.LRCPC2 = ((ISAR1 >> ISAR1_FIELDS::LRCPC) & IDFIELDMASK) >= 0b0010,
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.LRCPC3 = ((ISAR1 >> ISAR1_FIELDS::LRCPC) & IDFIELDMASK) >= 0b0011,
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};
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}
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} // namespace
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namespace SIGBUSTest {
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static bool* FaultArray {};
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__attribute__((naked)) static void atomic_load_u16(std::byte* Data) {
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asm volatile(R"(
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ldarh w1, [x0];
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ret;
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)" ::
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: "x1", "memory");
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}
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__attribute__((naked)) static void atomic_load_u32(std::byte* Data) {
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asm volatile(R"(
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ldar w1, [x0];
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ret;
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)" ::
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: "x1", "memory");
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}
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__attribute__((naked)) static void atomic_load_u64(std::byte* Data) {
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asm volatile(R"(
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ldar x1, [x0];
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ret;
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)" ::
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: "x1", "memory");
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}
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__attribute__((naked)) static void atomic_load_u128(std::byte* Data) {
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asm volatile(R"(
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ldaxp x1, x2, [x0];
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ret;
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)" ::
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: "x1", "x2", "x3", "memory");
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}
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__attribute__((naked)) static void atomic_set_u16(std::byte* Data, uint16_t value) {
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asm volatile(R"(
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.word 0x78e13002; // ldsetalh w1, w2, [x0];
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ret;
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)" ::
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: "memory");
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}
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__attribute__((naked)) static void atomic_set_u32(std::byte* Data, uint32_t value) {
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asm volatile(R"(
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.word 0xb8e13002; // ldsetal w1, w2, [x0];
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ret;
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)" ::
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: "memory");
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}
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__attribute__((naked)) static void atomic_set_u64(std::byte* Data, uint64_t value) {
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asm volatile(R"(
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.word 0xf8e13002; // ldsetal x1, x2, [x0];
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ret;
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)" ::
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: "memory");
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}
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__attribute__((naked)) static void atomic_set_u128_impl(__uint128_t expected, __uint128_t desired, std::byte* Data) {
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asm volatile(R"(
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.word 0x4860fc82; // caspal x0, x1, x2, x3, [x4];
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ret;
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)" ::
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: "memory");
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}
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static inline void atomic_set_u128(std::byte* Data, __uint128_t value) {
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atomic_set_u128_impl(*reinterpret_cast<__uint128_t*>(Data), value, Data);
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}
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static void HandleSIGBUS(int, siginfo_t* info, void* context) {
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FaultArray[reinterpret_cast<uintptr_t>(info->si_addr) & 63] = true;
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ucontext_t* ucontext = (ucontext_t*)context;
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mcontext_t* mcontext = &ucontext->uc_mcontext;
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// Skip the stlr.
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mcontext->pc += 4;
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}
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static bool CalculatedFaultOffsets {};
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static bool FaultOffset_16bit[64] {};
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static bool FaultOffset_32bit[64] {};
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static bool FaultOffset_64bit[64] {};
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static bool FaultOffset_128bit[64] {};
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static bool FaultOffset_RMW_16bit[64] {};
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static bool FaultOffset_RMW_32bit[64] {};
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static bool FaultOffset_RMW_64bit[64] {};
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static bool FaultOffset_RMW_128bit[64] {};
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static void RunFaultTests() {
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if (CalculatedFaultOffsets) {
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return;
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}
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struct sigaction act {};
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act.sa_sigaction = HandleSIGBUS;
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act.sa_flags = SA_SIGINFO;
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sigaction(SIGBUS, &act, &act);
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auto ptr = reinterpret_cast<std::byte*>(mmap(nullptr, 4096, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
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auto test_fault = [](bool* FaultOffsets, auto AccessFunction, std::byte* AccessArray) {
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FaultArray = FaultOffsets;
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for (size_t i = 0; i < 64; ++i) {
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AccessFunction(AccessArray + i);
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}
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};
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auto test_rmw_fault = [](bool* FaultOffsets, auto AccessFunction, std::byte* AccessArray) {
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FaultArray = FaultOffsets;
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for (size_t i = 0; i < 64; ++i) {
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AccessFunction(AccessArray + i, 1);
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}
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};
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test_fault(FaultOffset_16bit, atomic_load_u16, ptr);
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test_fault(FaultOffset_32bit, atomic_load_u32, ptr);
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test_fault(FaultOffset_64bit, atomic_load_u64, ptr);
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test_fault(FaultOffset_128bit, atomic_load_u128, ptr);
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auto TSOFacts = GetTSOEmulationFacts();
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if (TSOFacts.LSE) {
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test_rmw_fault(FaultOffset_RMW_16bit, atomic_set_u16, ptr);
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test_rmw_fault(FaultOffset_RMW_32bit, atomic_set_u32, ptr);
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test_rmw_fault(FaultOffset_RMW_64bit, atomic_set_u64, ptr);
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test_rmw_fault(FaultOffset_RMW_128bit, atomic_set_u128, ptr);
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}
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munmap(ptr, 4096);
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sigaction(SIGBUS, &act, nullptr);
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CalculatedFaultOffsets = true;
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}
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static void PrintSIGBUSInfo() {
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RunFaultTests();
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auto print_granule = [](const char* size, bool* FaultArray) {
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std::string output {};
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for (size_t i = 0; i < 64; ++i) {
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if (i && (i % 16 == 0)) {
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output += " ";
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}
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if (FaultArray[i]) {
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output += "\e[31m■\e[0m";
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} else {
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output += "\e[32m■\e[0m";
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}
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}
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fprintf(stdout, "%s: %s\n", size, output.c_str());
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};
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auto TSOFacts = GetTSOEmulationFacts();
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const bool RMWIsDifferent = TSOFacts.LSE && (memcmp(FaultOffset_16bit, FaultOffset_RMW_16bit, sizeof(FaultOffset_16bit)) != 0 ||
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memcmp(FaultOffset_32bit, FaultOffset_RMW_32bit, sizeof(FaultOffset_32bit)) != 0 ||
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memcmp(FaultOffset_64bit, FaultOffset_RMW_64bit, sizeof(FaultOffset_64bit)) != 0 ||
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memcmp(FaultOffset_128bit, FaultOffset_RMW_128bit, sizeof(FaultOffset_128bit)) != 0);
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if (!RMWIsDifferent) {
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fprintf(stdout, "Fault Granularity: Split every 16 bytes\n");
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} else {
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fprintf(stdout, "Load/Store Fault Granularity: Split every 16 bytes\n");
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}
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print_granule(" 16-bit", FaultOffset_16bit);
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print_granule(" 32-bit", FaultOffset_32bit);
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print_granule(" 64-bit", FaultOffset_64bit);
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print_granule("128-bit", FaultOffset_128bit);
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if (RMWIsDifferent) {
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fprintf(stdout, "RMW Atomic Fault Granularity: Split every 16 bytes\n");
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print_granule(" 16-bit", FaultOffset_RMW_16bit);
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print_granule(" 32-bit", FaultOffset_RMW_32bit);
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print_granule(" 64-bit", FaultOffset_RMW_64bit);
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print_granule("128-bit", FaultOffset_RMW_128bit);
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}
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}
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struct FirstFaultInformation {
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int32_t LoadStoreFaultAlignment {};
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int32_t RMWFaultAlignment {};
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};
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static FirstFaultInformation CalculateFirstFaultInformation() {
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RunFaultTests();
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FirstFaultInformation Info {};
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auto FindFirstFaultOffset = [](bool FaultOffsets[64]) -> int32_t {
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for (int32_t i = 0; i < 64; ++i) {
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if (FaultOffsets[i]) {
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return i;
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}
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}
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return -1;
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};
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Info.LoadStoreFaultAlignment = FindFirstFaultOffset(FaultOffset_16bit) + 1;
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Info.RMWFaultAlignment = FindFirstFaultOffset(FaultOffset_RMW_16bit) + 1;
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return Info;
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}
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} // namespace SIGBUSTest
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static void PrintTSOInfo() {
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auto TSOFacts = GetTSOEmulationFacts();
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FEX_CONFIG_OPT(TSOEnabled, TSOENABLED);
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FEX_CONFIG_OPT(MemcpySetTSOEnabled, MEMCPYSETTSOENABLED);
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FEX_CONFIG_OPT(VectorTSOEnabled, VECTORTSOENABLED);
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FEX_CONFIG_OPT(HalfBarrierTSOEnabled, HALFBARRIERTSOENABLED);
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FEX_CONFIG_OPT(StrictInProcessSplitLocks, STRICTINPROCESSSPLITLOCKS);
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const char* GPRMemoryTSOEmulation {};
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const char* MemcpyMemoryTSOEmulation {};
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const char* VectorMemoryTSOEmulation {};
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const char* UnalignedMemoryLoadStoreTSOEmulation {};
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const char* SplitLock16BEmulationType {};
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const char* SplitLock16BConfigurationType {};
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std::string UnalignedMemoryLoadStoreAlignmentGranularity {};
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std::string UnalignedRMWAlignmentGranularity {};
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if (TSOFacts.HardwareTSO) {
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GPRMemoryTSOEmulation = "\e[32mHardware TSO\e[0m";
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} else if (TSOFacts.LRCPC3) {
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GPRMemoryTSOEmulation = "\e[32mLRCPC3\e[0m";
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} else if (TSOFacts.LRCPC2) {
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GPRMemoryTSOEmulation = "\e[32mLRCPC2\e[0m";
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} else if (TSOFacts.LRCPC1) {
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GPRMemoryTSOEmulation = "\e[32mLRCPC\e[0m";
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} else {
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GPRMemoryTSOEmulation = "\e[31mAtomics\e[0m";
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}
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// Memcpy only uses Hardware TSO, LRCPC, and Atomics.
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if (TSOFacts.HardwareTSO) {
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MemcpyMemoryTSOEmulation = "\e[32mHardware TSO\e[0m";
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} else if (TSOFacts.LRCPC1) {
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MemcpyMemoryTSOEmulation = "\e[32mLRCPC\e[0m";
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} else {
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MemcpyMemoryTSOEmulation = "\e[31mAtomics\e[0m";
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}
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if (TSOFacts.HardwareTSO) {
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VectorMemoryTSOEmulation = "\e[32mHardware TSO\e[0m";
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} else if (TSOFacts.LRCPC3) {
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VectorMemoryTSOEmulation = "\e[32mLRCPC3\e[0m";
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} else {
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VectorMemoryTSOEmulation = "\e[31mHalf-Barriers\e[0m";
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}
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if (TSOFacts.HardwareTSO) {
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UnalignedMemoryLoadStoreTSOEmulation = "\e[32mHardware TSO\e[0m";
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} else {
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UnalignedMemoryLoadStoreTSOEmulation = "\e[31mHalf-Barriers\e[0m";
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}
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const auto FFInfo = SIGBUSTest::CalculateFirstFaultInformation();
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if (FFInfo.RMWFaultAlignment >= 64) {
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SplitLock16BEmulationType = "\e[32mHardware cacheline unaligned atomics\e[0m";
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SplitLock16BConfigurationType = "\e[32mTear-free\e[0m";
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} else {
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SplitLock16BEmulationType = TSOFacts.LSE ? "\e[31mTearing CAS loops\e[0m" : "\e[31mTearing LL/SC loops\e[0m";
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SplitLock16BConfigurationType = StrictInProcessSplitLocks() ? "In-process mutex" : "Tearing";
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}
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if (FFInfo.LoadStoreFaultAlignment != 1) {
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UnalignedMemoryLoadStoreAlignmentGranularity = fmt::format("\e[32m{}-byte\e[0m", FFInfo.LoadStoreFaultAlignment);
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} else {
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UnalignedMemoryLoadStoreAlignmentGranularity = TSOFacts.LSE2 ? "\e[32m16-byte\e[0m" : "\e[31mNatural alignment\e[0m";
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}
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if (FFInfo.LoadStoreFaultAlignment != FFInfo.RMWFaultAlignment) {
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if (FFInfo.LoadStoreFaultAlignment != 1) {
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UnalignedRMWAlignmentGranularity = fmt::format("\e[32m{}-byte\e[0m", FFInfo.RMWFaultAlignment);
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} else {
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UnalignedRMWAlignmentGranularity = TSOFacts.LSE2 ? "\e[32m16-byte\e[0m" : "\e[31mNatural alignment\e[0m";
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}
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}
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fprintf(stdout, "Hardware Features:\n");
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fprintf(stdout, "\tMemory atomics emulation method: %s\n", TSOFacts.LSE ? "\e[32mLSE\e[0m" : "\e[31mLL/SC\e[0m");
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fprintf(stdout, "\tUnaligned atomic memory granularity: %s\n", UnalignedMemoryLoadStoreAlignmentGranularity.c_str());
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if (FFInfo.LoadStoreFaultAlignment != FFInfo.RMWFaultAlignment) {
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fprintf(stdout, "\tUnaligned atomic RMW granularity: %s\n", UnalignedRMWAlignmentGranularity.c_str());
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}
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fprintf(stdout, "\tUnaligned memory loadstore emulation: %s\n", UnalignedMemoryLoadStoreTSOEmulation);
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fprintf(stdout, "\t16-Byte split-lock atomic emulation: %s\n", SplitLock16BEmulationType);
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fprintf(stdout, "\t64-Byte split-lock atomic emulation: %s\n", TSOFacts.LSE ? "\e[31mTearing CAS loops\e[0m" : "\e[31mTearing LL/SC loops\e[0m");
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fprintf(stdout, "\tGPR memory model emulation: %s\n", GPRMemoryTSOEmulation);
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fprintf(stdout, "\tMemcpy memory model emulation: %s\n", MemcpyMemoryTSOEmulation);
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fprintf(stdout, "\tVector memory model emulation: %s\n", VectorMemoryTSOEmulation);
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fprintf(stdout, "\nConfiguration:\n");
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fprintf(stdout, "\tTSO Emulation: %s\n", TSOEnabled() ? "Enabled" : "Disabled");
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fprintf(stdout, "\tMemcpy TSO Emulation: %s\n", TSOEnabled() && MemcpySetTSOEnabled() ? "Enabled" : "Disabled");
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fprintf(stdout, "\tVector TSO Emulation: %s\n", TSOEnabled() && VectorTSOEnabled() ? "Enabled" : "Disabled");
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fprintf(stdout, "\tHalf-barrier unaligned TSO emulation: %s\n", TSOEnabled() && HalfBarrierTSOEnabled() ? "Enabled" : "Disabled");
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fprintf(stdout, "\t16-Byte strict split-lock emulation: %s\n", SplitLock16BConfigurationType);
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fprintf(stdout, "\t64-Byte strict split-lock emulation: %s\n", StrictInProcessSplitLocks() ? "In-process mutex" : "Tearing");
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}
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static void PrintIDRegInfo() {
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auto Features = FEX::GetCPUFeaturesFromIDRegisters();
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fextl::string features {};
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features += fmt::format("isar0=0x{:x},", Features.ISAR0.Get());
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features += fmt::format("isar1=0x{:x},", Features.ISAR1.Get());
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features += fmt::format("isar2=0x{:x},", Features.ISAR2.Get());
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features += fmt::format("pfr0=0x{:x},", Features.PFR0.Get());
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features += fmt::format("pfr1=0x{:x},", Features.PFR1.Get());
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features += fmt::format("midr=0x{:x},", Features.MIDR.Get());
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features += fmt::format("mmfr0=0x{:x},", Features.MMFR0.Get());
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features += fmt::format("mmfr1=0x{:x},", Features.MMFR1.Get());
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features += fmt::format("mmfr2=0x{:x},", Features.MMFR2.Get());
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features += fmt::format("mmfr3=0x{:x},", Features.MMFR3.Get());
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features += fmt::format("zfr0=0x{:x},", Features.ZFR0.Get());
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features += fmt::format("dczid=0x{:x},", Features.DCZID.Get());
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features += fmt::format("svevl=0x{:x}", Features.SVEVL.Get());
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fprintf(stderr, "Features: '%s'\n", features.c_str());
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}
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#endif
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int main(int argc, char** argv, char** envp) {
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FEX::Config::InitializeConfigs(FEX::Config::PortableInformation {});
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FEXCore::Config::Initialize();
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FEXCore::Config::AddLayer(FEX::Config::CreateGlobalMainLayer());
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FEXCore::Config::AddLayer(FEX::Config::CreateMainLayer());
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// No FEX arguments passed through command line
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FEXCore::Config::AddLayer(FEX::Config::CreateEnvironmentLayer(envp));
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// Load the arguments
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optparse::OptionParser Parser = optparse::OptionParser().description("Simple application to get a couple of FEX options");
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Parser.add_option("--install-prefix").action("store_true").help("Print the FEX install prefix");
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Parser.add_option("--app").help("Load an application profile for this application if it exists");
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Parser.add_option("--current-rootfs").action("store_true").help("Print the directory that contains the FEX rootfs. Mounted in the case of squashfs");
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#ifdef ARCHITECTURE_arm64
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Parser.add_option("--tso-emulation-info").action("store_true").help("Print how FEX is emulating the x86-TSO memory model.");
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Parser.add_option("--test-fault-granularity").action("store_true").help("Show SIGBUS fault granularity");
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Parser.add_option("--identification-reg-info").action("store_true").help("Print identification registers");
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Parser.add_option("-e", "--all-emu-info").action("store_true").help("Prints all relevant emulation related information");
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#endif
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Parser.add_option("--version").action("store_true").help("Print the installed FEX-Emu version");
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optparse::Values Options = Parser.parse_args(argc, argv);
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if (Options.is_set_by_user("app")) {
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// Load the application config if one was provided
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const auto ProgramName = FHU::Filesystem::GetFilename(Options["app"]);
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FEXCore::Config::AddLayer(FEX::Config::CreateAppLayer(ProgramName, FEXCore::Config::LayerType::LAYER_GLOBAL_APP));
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FEXCore::Config::AddLayer(FEX::Config::CreateAppLayer(ProgramName, FEXCore::Config::LayerType::LAYER_LOCAL_APP));
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auto SteamID = getenv("SteamAppId");
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if (SteamID) {
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// If a SteamID exists then let's search for Steam application configs as well.
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// We want to key off both the SteamAppId number /and/ the executable since we may not want to thunk all binaries.
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const auto SteamAppName = fextl::fmt::format("Steam_{}_{}", SteamID, ProgramName);
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FEXCore::Config::AddLayer(FEX::Config::CreateAppLayer(SteamAppName, FEXCore::Config::LayerType::LAYER_GLOBAL_STEAM_APP));
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FEXCore::Config::AddLayer(FEX::Config::CreateAppLayer(SteamAppName, FEXCore::Config::LayerType::LAYER_LOCAL_STEAM_APP));
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}
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}
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FEXCore::Config::Load();
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|
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// Reload the meta layer
|
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FEXCore::Config::ReloadMetaLayer();
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|
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const bool IsAllEmuInfo = Options.is_set_by_user("all_emu_info");
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|
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if (IsAllEmuInfo || Options.is_set_by_user("version")) {
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fprintf(stdout, GIT_DESCRIBE_STRING "\n");
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}
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|
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if (Options.is_set_by_user("install_prefix")) {
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char SelfPath[PATH_MAX];
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auto Result = readlink("/proc/self/exe", SelfPath, PATH_MAX);
|
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if (Result == -1) {
|
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Result = 0;
|
|
}
|
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auto InstallPrefix = std::filesystem::path(&SelfPath[0], &SelfPath[Result]).parent_path().parent_path().string();
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fprintf(stdout, "%s\n", InstallPrefix.c_str());
|
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}
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|
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if (Options.is_set_by_user("current_rootfs")) {
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int ServerFD = FEXServerClient::ConnectToServer();
|
|
if (ServerFD != -1) {
|
|
auto RootFS = FEXServerClient::RequestRootFSPath(ServerFD);
|
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if (!RootFS.empty()) {
|
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fprintf(stdout, "%s\n", RootFS.c_str());
|
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}
|
|
}
|
|
}
|
|
|
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#ifdef ARCHITECTURE_arm64
|
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if (IsAllEmuInfo || Options.is_set_by_user("tso_emulation_info")) {
|
|
PrintTSOInfo();
|
|
}
|
|
|
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if (IsAllEmuInfo || Options.is_set_by_user("identification_reg_info")) {
|
|
PrintIDRegInfo();
|
|
}
|
|
|
|
if (IsAllEmuInfo || Options.is_set_by_user("test_fault_granularity")) {
|
|
SIGBUSTest::PrintSIGBUSInfo();
|
|
}
|
|
#endif
|
|
|
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return 0;
|
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}
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