mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 12:00:17 +02:00
221 lines
6.3 KiB
JSON
221 lines
6.3 KiB
JSON
{
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"Features": {
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"Bitness": 64,
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"EnabledHostFeatures": [],
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"DisabledHostFeatures": [
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"SVE128",
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"SVE256",
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"FLAGM",
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"FLAGM2",
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"CRYPTO"
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],
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"Comment": [
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"Look at the official documentation for more information about this layout.",
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"imm of each string comparison operation changes behaviour of the operation.",
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"[1:0] - Source Data Format",
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" - 00b: Unsigned bytes",
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" - 01b: Unsigned words",
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" - 10b: Signed bytes",
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" - 11b: Signed words",
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"[3:2] - Aggregation Operation",
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" - 00b: Equal Any",
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" - 01b: Range",
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" - 10b: Equal Each",
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" - 11b: Equal Ordered",
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"[5:4] - Polarity",
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" - 00b: Positive Polarity (IntRes2 = IntRes1)",
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" - 01b: Negative Polarity (IntRes2 = -1 ^ IntRes1)",
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" - 10b: Positive Masked (IntRes2 = IntRes1)",
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" - 11b: Negative Masked (IntRes2[i] = ~IntRes1[i])",
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"[6] - Output selection",
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" - 0b: ECX = LSB",
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" - 1b: ECX = MSB",
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"[7] - Reserved"
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]
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},
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"Instructions": {
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"pcmpestrm xmm0, xmm1, 0_0_00_00_00b": {
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"ExpectedInstructionCount": 35,
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"Comment": [
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"0x66 0x0f 0x3A 0x60"
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],
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"ExpectedArm64ASM": [
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"mov x0, x4",
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"mov x1, x6",
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"mrs x2, nzcv",
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"str w2, [x28, #728]",
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"stp x4, x5, [x28, #8]",
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"stp x6, x7, [x28, #24]",
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"str x8, [x28, #40]",
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"stp x16, x17, [x28, #104]",
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"sub sp, sp, #0x70 (112)",
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"mov x2, sp",
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"st1 {v2.2d, v3.2d}, [x2], #32",
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"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x2], #64",
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"str x30, [x2], #16",
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"mov x2, v16.d[0]",
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"mov x3, v16.d[1]",
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"mov x4, v17.d[0]",
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"mov x5, v17.d[1]",
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"mov w6, #0x0",
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"ldr x7, [x28, #1552]",
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"blr x7",
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"ldr w4, [x28, #728]",
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"msr nzcv, x4",
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"ldp x4, x5, [x28, #8]",
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"ldp x6, x7, [x28, #24]",
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"ldr x8, [x28, #40]",
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"ldp x16, x17, [x28, #104]",
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"ld1 {v2.2d, v3.2d}, [sp], #32",
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"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
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"ldr x30, [sp], #16",
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"mov w20, w0",
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"mov w27, #0x0",
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"uxth w0, w20",
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"fmov s16, w0",
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"mov w26, #0x1",
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"msr nzcv, x20"
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]
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},
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"pcmpestri xmm0, xmm1, 0_0_00_00_00b": {
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"ExpectedInstructionCount": 42,
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"Comment": [
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"0x66 0x0f 0x3A 0x61"
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],
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"ExpectedArm64ASM": [
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"mov x0, x4",
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"mov x1, x6",
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"mrs x2, nzcv",
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"str w2, [x28, #728]",
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"stp x4, x5, [x28, #8]",
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"stp x6, x7, [x28, #24]",
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"str x8, [x28, #40]",
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"stp x16, x17, [x28, #104]",
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"sub sp, sp, #0x70 (112)",
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"mov x2, sp",
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"st1 {v2.2d, v3.2d}, [x2], #32",
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"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x2], #64",
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"str x30, [x2], #16",
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"mov x2, v16.d[0]",
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"mov x3, v16.d[1]",
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"mov x4, v17.d[0]",
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"mov x5, v17.d[1]",
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"mov w6, #0x0",
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"ldr x7, [x28, #1552]",
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"blr x7",
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"ldr w4, [x28, #728]",
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"msr nzcv, x4",
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"ldp x4, x5, [x28, #8]",
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"ldp x6, x7, [x28, #24]",
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"ldr x8, [x28, #40]",
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"ldp x16, x17, [x28, #104]",
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"ld1 {v2.2d, v3.2d}, [sp], #32",
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"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
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"ldr x30, [sp], #16",
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"mov w20, w0",
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"mov w27, #0x0",
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"uxth w21, w20",
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"mov w22, #0x10",
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"lsr w0, w21, #0",
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"cmp w0, #0x0 (0)",
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"rbit w0, w0",
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"clz w23, w0",
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"csinv w23, w23, wzr, ne",
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"cmp x21, #0x0 (0)",
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"csel x5, x22, x23, eq",
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"mov w26, #0x1",
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"msr nzcv, x20"
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]
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},
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"pcmpistrm xmm0, xmm1, 0_0_00_00_00b": {
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"ExpectedInstructionCount": 33,
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"Comment": [
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"0x66 0x0f 0x3A 0x62"
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],
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"ExpectedArm64ASM": [
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"mrs x0, nzcv",
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"str w0, [x28, #728]",
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"stp x4, x5, [x28, #8]",
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"stp x6, x7, [x28, #24]",
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"str x8, [x28, #40]",
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"stp x16, x17, [x28, #104]",
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"sub sp, sp, #0x70 (112)",
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"mov x0, sp",
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"st1 {v2.2d, v3.2d}, [x0], #32",
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"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
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"str x30, [x0], #16",
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"mov x0, v16.d[0]",
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"mov x1, v16.d[1]",
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"mov x2, v17.d[0]",
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"mov x3, v17.d[1]",
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"mov w4, #0x0",
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"ldr x5, [x28, #1560]",
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"blr x5",
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"ldr w4, [x28, #728]",
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"msr nzcv, x4",
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"ldp x4, x5, [x28, #8]",
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"ldp x6, x7, [x28, #24]",
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"ldr x8, [x28, #40]",
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"ldp x16, x17, [x28, #104]",
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"ld1 {v2.2d, v3.2d}, [sp], #32",
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"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
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"ldr x30, [sp], #16",
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"mov w20, w0",
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"mov w27, #0x0",
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"uxth w0, w20",
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"fmov s16, w0",
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"mov w26, #0x1",
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"msr nzcv, x20"
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]
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},
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"pcmpistri xmm0, xmm1, 0_0_00_00_00b": {
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"ExpectedInstructionCount": 40,
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"Comment": [
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"0x66 0x0f 0x3A 0x63"
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],
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"ExpectedArm64ASM": [
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"mrs x0, nzcv",
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"str w0, [x28, #728]",
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"stp x4, x5, [x28, #8]",
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"stp x6, x7, [x28, #24]",
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"str x8, [x28, #40]",
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"stp x16, x17, [x28, #104]",
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"sub sp, sp, #0x70 (112)",
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"mov x0, sp",
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"st1 {v2.2d, v3.2d}, [x0], #32",
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"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
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"str x30, [x0], #16",
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"mov x0, v16.d[0]",
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"mov x1, v16.d[1]",
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"mov x2, v17.d[0]",
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"mov x3, v17.d[1]",
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"mov w4, #0x0",
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"ldr x5, [x28, #1560]",
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"blr x5",
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"ldr w4, [x28, #728]",
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"msr nzcv, x4",
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"ldp x4, x5, [x28, #8]",
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"ldp x6, x7, [x28, #24]",
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"ldr x8, [x28, #40]",
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"ldp x16, x17, [x28, #104]",
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"ld1 {v2.2d, v3.2d}, [sp], #32",
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"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
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"ldr x30, [sp], #16",
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"mov w20, w0",
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"mov w27, #0x0",
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"uxth w21, w20",
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"mov w22, #0x10",
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"lsr w0, w21, #0",
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"cmp w0, #0x0 (0)",
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"rbit w0, w0",
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"clz w23, w0",
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"csinv w23, w23, wzr, ne",
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"cmp x21, #0x0 (0)",
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"csel x5, x22, x23, eq",
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"mov w26, #0x1",
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"msr nzcv, x20"
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]
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}
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}
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}
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