Alyssa Rosenzweig 2dcae23776 Arm64Emitter: Dedicate registers for PF/AF ...

Many flag-generating instructions like cmp need to save calculations for
deferred PF and AF flag calculation. Currently, they require a store per flag,
which is prohibitively expensive for hot instructions like cmp. By instead
pinning PF/AF temporary results to registers (x26/x27 by convention here), we
eliminate many stores altogether and turn the rest into zero-cycle moves (on
64-bit at least, this isn't optimal for 32-bit emulation due to CTX->GetGPRSize
shenanigans, need to check if this requirement can be lifted..).

To implement, we model as SRA and then the existing SRA code is able to generate
good code with little manual tuning. (Future work will get us to excellent code
with more tuning ;) ).

The tradeoff is reducing the working dynamic GPR set by 2 registers, which might
increase spilling in some cases. I think it's worth it in practice, though.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2023-11-17 17:37:24 -04:00

..

Crypto.cpp

OpcodeDispatcher: Optimize three sha instructions

2023-11-13 18:38:02 -08:00

Flags.cpp

Arm64Emitter: Dedicate registers for PF/AF

2023-11-17 17:37:24 -04:00

Vector.cpp

OpcodeDispatcher: Use DeriveOp

2023-11-07 12:05:00 -04:00

X87.cpp

OpcodeDispatcher: Use predicated neg for x87 fild

2023-11-12 17:32:24 -04:00

X87F64.cpp

OpcodeDispatcher: Use DeriveOp

2023-11-07 12:05:00 -04:00