mirror of
https://github.com/FEX-Emu/FEX.git
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Paulo Matos
2b4ec88dae
This follows discussions from #3413. Followup commits add clang-format file, script and blame ignore lists.
68 lines
2.0 KiB
C++
68 lines
2.0 KiB
C++
// SPDX-License-Identifier: MIT
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/*
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$info$
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tags: ir|opts
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$end_info$
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*/
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#pragma once
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#include "Interface/IR/PassManager.h"
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#include <memory>
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#include <stdint.h>
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namespace FEXCore::IR {
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class RegisterAllocationData;
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struct RegisterAllocationDataDeleter;
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struct RegisterClassType;
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class RegisterAllocationPass : public FEXCore::IR::Pass {
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public:
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bool HasFullRA() const {
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return HadFullRA;
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}
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virtual void AllocateRegisterSet(uint32_t ClassCount) = 0;
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virtual void AddRegisters(FEXCore::IR::RegisterClassType Class, uint32_t RegisterCount) = 0;
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/**
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* @brief Adds a conflict between the two registers (and their respective classes) so if one is allocated then the other can not be
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* allocated in the same live range.
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*
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* Conflict is added both directions, so only necessary to add a conflict one way
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*
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* ex:
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* AddRegisters(GPRClass, 2); -> {x0, x1} added to register class GPR
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* AddRegisters(PairClass, 1); -> {{x0, x1}} pair added to class GPR
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* AddRegisterConflict(GPRClass, 0, PairClass, 0); -> Make sure the pair interferes with x0
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* AddRegisterConflict(GPRClass, 1, PairClass, 1); -> Make sure the pair interferes with x1
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*/
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virtual void AddRegisterConflict(FEXCore::IR::RegisterClassType ClassConflict, uint32_t RegConflict, FEXCore::IR::RegisterClassType Class,
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uint32_t Reg) = 0;
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/**
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* @name Inference graph handling
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* @{ */
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/**
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* @brief Returns the register and class map array
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*/
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virtual RegisterAllocationData* GetAllocationData() = 0;
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/**
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* @brief Returns and transfers ownership of the register and class map array
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*/
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virtual std::unique_ptr<RegisterAllocationData, RegisterAllocationDataDeleter> PullAllocationData() = 0;
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/** @} */
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protected:
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bool HasSpills {};
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// Debug option to disable split slot reuse
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// Can be useful for testing if there is a bug with spill slots
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constexpr static bool ReuseSpillSlots {true};
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uint32_t SpillSlotCount {};
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bool HadFullRA {};
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};
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} // namespace FEXCore::IR
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