mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 13:00:15 +02:00
Alyssa Rosenzweig
27c8bf3021
(except for when we explicitly enable AFP). Since AFP gets saved/restored, we get `msr fpcr` garbage in random instructions when AFP is enabled. Explicitly disable everywhere since it's not worth our time to triage which files might hit that path. Fixes instcountci on AFP-supporting hosts now that we have AFP enabled. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
312 lines
7.9 KiB
JSON
312 lines
7.9 KiB
JSON
{
|
|
"Features": {
|
|
"Bitness": 64,
|
|
"EnabledHostFeatures": [],
|
|
"DisabledHostFeatures": [
|
|
"SVE128",
|
|
"SVE256",
|
|
"AFP",
|
|
"RPRES"
|
|
]
|
|
},
|
|
"Comment": [
|
|
"These 3DNow! instructions are optimal assuming that FEX doesn't SRA MMX registers",
|
|
"This accounts for the overhead of loading and storing the registers in each instruction",
|
|
"Could technically save some instructions by using SRA for MMX registers."
|
|
],
|
|
"Instructions": {
|
|
"pi2fw mm0, mm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"0x0f 0x0f 0x0c"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"uzp1 v2.4h, v2.4h, v2.4h",
|
|
"sxtl v2.4s, v2.4h",
|
|
"scvtf v2.2s, v2.2s",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pi2fd mm0, mm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"0x0f 0x0f 0x0d"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"scvtf v2.2s, v2.2s",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pf2iw mm0, mm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"0x0f 0x0f 0x1c"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"fcvtzs v2.2s, v2.2s",
|
|
"uzp1 v2.4h, v2.4h, v2.4h",
|
|
"sxtl v2.4s, v2.4h",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pf2id mm0, mm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"0x0f 0x0f 0x1d"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"fcvtzs v2.2s, v2.2s",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pfrcpv mm0, mm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"0x0f 0x0f 0x86"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"fmov v0.4s, #0x70 (1.0000)",
|
|
"fdiv v2.4s, v0.4s, v2.4s",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pfrsqrtv mm0, mm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"0x0f 0x0f 0x87"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"fmov v0.4s, #0x70 (1.0000)",
|
|
"fsqrt v1.4s, v2.4s",
|
|
"fdiv v2.4s, v0.4s, v1.4s",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pfnacc mm0, mm1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x0f 0x0f 0x8a",
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #768]",
|
|
"ldr d3, [x28, #784]",
|
|
"uzp1 v4.2s, v2.2s, v3.2s",
|
|
"uzp2 v2.2s, v2.2s, v3.2s",
|
|
"fsub v2.4s, v4.4s, v2.4s",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pfpnacc mm0, mm1": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "0x0f 0x0f 0x8e",
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #768]",
|
|
"ldr d3, [x28, #784]",
|
|
"dup v4.2s, v2.s[1]",
|
|
"fsub s2, s2, s4",
|
|
"faddp v3.4s, v3.4s, v3.4s",
|
|
"mov v2.s[1], v3.s[0]",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pfcmpge mm0, mm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x0f 0x0f 0x90",
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"ldr d3, [x28, #768]",
|
|
"fcmge v2.4s, v3.4s, v2.4s",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pfmin mm0, mm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x0f 0x0f 0x94",
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"ldr d3, [x28, #768]",
|
|
"fcmgt v0.4s, v3.4s, v2.4s",
|
|
"bif v2.16b, v3.16b, v0.16b",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pfrcp mm0, mm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"0x0f 0x0f 0x96"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"fmov s0, #0x70 (1.0000)",
|
|
"fdiv s2, s0, s2",
|
|
"dup v2.2s, v2.s[0]",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pfrsqrt mm0, mm1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"0x0f 0x0f 0x97"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"fmov s0, #0x70 (1.0000)",
|
|
"fsqrt s1, s2",
|
|
"fdiv s2, s0, s1",
|
|
"dup v2.2s, v2.s[0]",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pfsub mm0, mm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x0f 0x0f 0x9a",
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"ldr d3, [x28, #768]",
|
|
"fsub v2.4s, v3.4s, v2.4s",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pfadd mm0, mm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x0f 0x0f 0x9e",
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"ldr d3, [x28, #768]",
|
|
"fadd v2.4s, v3.4s, v2.4s",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pfcmpgt mm0, mm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x0f 0x0f 0xa0",
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"ldr d3, [x28, #768]",
|
|
"fcmgt v2.4s, v3.4s, v2.4s",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pfmax mm0, mm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x0f 0x0f 0xa4",
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"ldr d3, [x28, #768]",
|
|
"fcmgt v0.4s, v3.4s, v2.4s",
|
|
"bit v2.16b, v3.16b, v0.16b",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pfrcpit1 mm0, mm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x0f 0xa6",
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pfrcpit1 mm0, mm0": {
|
|
"ExpectedInstructionCount": 0,
|
|
"Comment": "0x0f 0x0f 0xa6",
|
|
"ExpectedArm64ASM": []
|
|
},
|
|
"pfrsqit1 mm0, mm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x0f 0xa7",
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pfrsqit1 mm0, mm0": {
|
|
"ExpectedInstructionCount": 0,
|
|
"Comment": "0x0f 0x0f 0xa7",
|
|
"ExpectedArm64ASM": []
|
|
},
|
|
"pfsubr mm0, mm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x0f 0x0f 0xaa",
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"ldr d3, [x28, #768]",
|
|
"fsub v2.4s, v2.4s, v3.4s",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pfcmpeq mm0, mm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x0f 0x0f 0xb0",
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"ldr d3, [x28, #768]",
|
|
"fcmeq v2.4s, v3.4s, v2.4s",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pfmul mm0, mm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x0f 0x0f 0xb4",
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"ldr d3, [x28, #768]",
|
|
"fmul v2.4s, v3.4s, v2.4s",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pfrcpit2 mm0, mm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x0f 0xb6",
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pfrcpit2 mm0, mm0": {
|
|
"ExpectedInstructionCount": 0,
|
|
"Comment": "0x0f 0x0f 0xb6",
|
|
"ExpectedArm64ASM": []
|
|
},
|
|
"db 0x0f, 0x0f, 0xc1, 0xb7": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"nasm doesn't support emitting this instruction",
|
|
"pmulhrw mm0, mm1",
|
|
"0x0f 0x0f 0xb7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #768]",
|
|
"ldr d3, [x28, #784]",
|
|
"smull v2.4s, v2.4h, v3.4h",
|
|
"movi v3.4s, #0x80, lsl #8",
|
|
"add v2.4s, v2.4s, v3.4s",
|
|
"shrn v2.4h, v2.4s, #16",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pswapd mm0, mm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x0f 0x0f 0xbb",
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"rev64 v2.2s, v2.2s",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pavgusb mm0, mm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x0f 0x0f 0xbf",
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"ldr d3, [x28, #768]",
|
|
"urhadd v2.16b, v3.16b, v2.16b",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
}
|
|
}
|
|
}
|