Alyssa Rosenzweig 1eb470083c IR: merge div/rem opcodes ...

it's simpler & faster to calculate both together, matching the x86 semantic.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2025-06-10 17:08:20 -04:00

..

Common

Softfloat: Remove warnings

2025-04-07 15:22:24 -07:00

Interface

IR: merge div/rem opcodes

2025-06-10 17:08:20 -04:00

Utils

FEXCore/Utils: Implement a new VL64Pair struct type

2025-04-30 15:36:49 -07:00

CMakeLists.txt

IR: drop RA validation

2025-05-16 15:18:06 -04:00