LC 1d8b6df630 [SVE256] Vector: Handle SSE insertion properly for various ALU operations ...

See #3799 for the bulk of the issue explanation. Ensures that emulated
SSE operation on aarch64 don't end up obliterating the upper 128-bit
lane when SVE-256 is present (Adv. SIMD operations zero-extend)

Knocks out quite a few SSE instructions right off the jump.

2026-06-16 22:26:28 -04:00

..

AVX_128.cpp

FEXCore: Fixes VEX float compare operations

2026-02-23 15:45:44 -08:00

BaseTables.h

FEXCore: Revert literal optimization from #4884

2025-12-22 10:00:55 -08:00

Crypto.cpp

OpcodeDispatcher: Default alignment parameters for store helpers

2025-10-06 11:04:12 -04:00

DDDTables.h

FEXCore/OpcodeDispatcher: Removes tuple usage for Dispatch tables

2025-07-16 13:57:16 -07:00

Flags.cpp

FEXCore: Switch constant emission to default to NoPad

2025-12-29 11:45:51 -08:00

H0F3ATables.h

X86Tables: Converts H0F3A table to constexpr

2025-08-27 12:24:24 -07:00

H0F38Tables.h

X86Tables: Converts H0F38 table to constexpr

2025-08-27 12:24:24 -07:00

PrimaryGroupTables.h

OpcodeDispatcher: Implement support for CALLF/RETF

2025-08-13 16:18:12 -07:00

SecondaryGroupTables.h

OpcodeDispatcher: Implement support for imm extrq/insertq

2025-10-03 13:05:43 -07:00

SecondaryModRMTables.h

X86Tables: Move Second ModRM table to be constexpr

2025-08-27 12:24:25 -07:00

SecondaryTables.h

Fix build failure.

2026-05-22 15:33:41 -07:00

Vector.cpp

[SVE256] Vector: Handle SSE insertion properly for various ALU operations

2026-06-16 22:26:28 -04:00

VEXTables.h

FEXCore/OpcodeDispatcher: Removes tuple usage for Dispatch tables

2025-07-16 13:57:16 -07:00

X87.cpp

Merge pull request #5446 from bylaws/claudefix4

2026-04-30 14:40:41 -07:00

X87F64.cpp

Merge pull request #5448 from bylaws/claudefix6

2026-04-30 14:42:08 -07:00