Alyssa Rosenzweig 1ad928dc2c IR: Add special NZCV "flag" ...

Reserve 4 bytes of "flags" to model the 32-bit arm64 NZCV register, so
we can start porting FEX's flag handling code over to using NZCV without
needing the whole compiler to be aware of instructions that might
clobber host flags.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2023-08-02 12:38:00 -04:00

..

Config

FEXCore: Remove erroneous asserts in the project

2023-07-28 13:36:05 -07:00

Context

Context: Make alias for code invalidation functor

2023-07-27 18:59:15 -04:00

Core

IR: Add special NZCV "flag"

2023-08-02 12:38:00 -04:00

GDBJIT

SourcecodeResolver: Convert string to fextl

2023-03-16 03:21:45 -07:00

HLE/Thunks

Thunks: Mostly reverts #2672

2023-05-18 15:50:55 -07:00

IR

IR: Adds support for VUABDL2 operation

2023-07-28 10:56:59 -07:00