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Ryan Houdek
199cfd76d8
I had to change how blocks are represented to make it easier to parse This required a fairly substantial refactor that makes it so blocks are represented differently and we can walk them sequentially. This will make future analysis easier to deal with. Had to rewrite the passes and core's parsing of the IR afterwards. Moved RA in to a optimization pass to be shared between the JIT backends This works because x86-64 and AArch64 RA can be identical. Still doesn't support PHI nodes or spilling correctly, this is the first step in the process of getting there.
31 lines
508 B
C++
31 lines
508 B
C++
#pragma once
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#include <FEXCore/IR/IntrusiveIRList.h>
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#include <memory>
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#include <vector>
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namespace FEXCore::IR {
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class OpDispatchBuilder;
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class Pass {
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public:
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virtual ~Pass() = default;
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virtual bool Run(OpDispatchBuilder *Disp) = 0;
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};
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class PassManager final {
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public:
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void AddDefaultPasses();
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void AddDefaultValidationPasses();
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void InsertPass(Pass *Pass) {
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Passes.emplace_back(Pass);
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}
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bool Run(OpDispatchBuilder *Disp);
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private:
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std::vector<std::unique_ptr<Pass>> Passes;
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};
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}
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