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Ryan Houdek
199cfd76d8
I had to change how blocks are represented to make it easier to parse This required a fairly substantial refactor that makes it so blocks are represented differently and we can walk them sequentially. This will make future analysis easier to deal with. Had to rewrite the passes and core's parsing of the IR afterwards. Moved RA in to a optimization pass to be shared between the JIT backends This works because x86-64 and AArch64 RA can be identical. Still doesn't support PHI nodes or spilling correctly, this is the first step in the process of getting there.
33 lines
1.3 KiB
C++
33 lines
1.3 KiB
C++
#include "Interface/IR/Passes.h"
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#include "Interface/IR/Passes/RegisterAllocationPass.h"
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#include "Interface/IR/PassManager.h"
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namespace FEXCore::IR {
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void PassManager::AddDefaultPasses() {
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Passes.emplace_back(std::unique_ptr<FEXCore::IR::Pass>(CreateConstProp()));
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// XXX: Causes corrupted output in test app
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// Passes.emplace_back(std::unique_ptr<FEXCore::IR::Pass>(CreateRedundantContextLoadElimination()));
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Passes.emplace_back(std::unique_ptr<FEXCore::IR::Pass>(CreateRedundantFlagCalculationEliminination()));
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Passes.emplace_back(std::unique_ptr<FEXCore::IR::Pass>(CreateSyscallOptimization()));
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Passes.emplace_back(std::unique_ptr<FEXCore::IR::Pass>(CreatePassDeadContextStoreElimination()));
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// If the IR is compacted post-RA then the node indexing gets messed up and the backend isn't able to find the register assigned to a node
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// Compact before IR, don't worry about RA generating spills/fills
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Passes.emplace_back(std::unique_ptr<FEXCore::IR::Pass>(CreateIRCompaction()));
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}
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void PassManager::AddDefaultValidationPasses() {
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// Passes.emplace_back(std::unique_ptr<FEXCore::IR::Pass>(Validation::CreateIRValidation()));
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}
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bool PassManager::Run(OpDispatchBuilder *Disp) {
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bool Changed = false;
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for (auto const &Pass : Passes) {
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Changed |= Pass->Run(Disp);
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}
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return Changed;
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}
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}
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