mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 10:00:16 +02:00
Ryan Houdek
199cfd76d8
I had to change how blocks are represented to make it easier to parse This required a fairly substantial refactor that makes it so blocks are represented differently and we can walk them sequentially. This will make future analysis easier to deal with. Had to rewrite the passes and core's parsing of the IR afterwards. Moved RA in to a optimization pass to be shared between the JIT backends This works because x86-64 and AArch64 RA can be identical. Still doesn't support PHI nodes or spilling correctly, this is the first step in the process of getting there.
565 lines
9.3 KiB
JSON
565 lines
9.3 KiB
JSON
{
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"Defines": [
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"constexpr static uint8_t COND_EQ = 0",
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"constexpr static uint8_t COND_NEQ = 1",
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"constexpr static uint8_t COND_CS = 2",
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"constexpr static uint8_t COND_CC = 3",
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"constexpr static uint8_t COND_MI = 4",
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"constexpr static uint8_t COND_PL = 5",
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"constexpr static uint8_t COND_VS = 6",
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"constexpr static uint8_t COND_VC = 7",
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"constexpr static uint8_t COND_HI = 8",
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"constexpr static uint8_t COND_LS = 9",
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"constexpr static uint8_t COND_GE = 10",
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"constexpr static uint8_t COND_LT = 11",
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"constexpr static uint8_t COND_GT = 12",
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"constexpr static uint8_t COND_LE = 13"
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],
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"Ops": {
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"Dummy": {
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},
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"IRHeader": {
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"Args": [
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"uint64_t", "Entry",
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"OrderedNodeWrapper", "Blocks",
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"uint32_t", "BlockCount"
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]
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},
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"CodeBlock": {
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"SSAArgs": "3",
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"SSANames": [
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"Begin",
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"Last",
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"Next"
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]
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},
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"Constant": {
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"HasDest": true,
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"FixedDestSize": "8",
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"Args": [
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"uint64_t", "Constant"
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]
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},
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"BeginBlock": {},
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"EndBlock": {
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"Args": [
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"uint64_t", "RIPIncrement"
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]
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},
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"Break": {
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"Args": [
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"uint8_t", "Reason",
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"uint8_t", "Literal"
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]
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},
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"EndFunction": {},
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"ExitFunction": {},
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"Jump": {
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"DispatcherUnary": true,
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"SSAArgs": "1"
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},
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"CondJump": {
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"SSAArgs": "2"
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},
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"Mov": {
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"HasDest": true,
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"DestSize": "GetOpSize(ssa0)",
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"SSAArgs": "1"
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},
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"CycleCounter": {
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"HasDest": true,
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"FixedDestSize": "8"
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},
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"LoadContext": {
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"HasDest": true,
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"DestSize": "Size",
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"Args": [
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"uint8_t", "Size",
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"uint32_t", "Offset"
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]
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},
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"StoreContext": {
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"SSAArgs": "1",
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"Args": [
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"uint8_t", "Size",
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"uint32_t", "Offset"
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]
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},
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"SpillRegister": {
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"SSAArgs": "1",
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"Args": [
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"uint32_t", "Slot",
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"RegisterClassType", "Class"
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]
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},
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"FillRegister": {
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"HasDest": true,
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"Args": [
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"uint32_t", "Slot",
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"RegisterClassType", "Class"
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]
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},
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"LoadFlag": {
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"HasDest": true,
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"DestSize": "1",
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"Args": [
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"uint32_t", "Flag"
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]
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},
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"StoreFlag": {
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"SSAArgs": "1",
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"Args": [
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"uint32_t", "Flag"
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]
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},
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"Syscall": {
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"HasDest": true,
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"FixedDestSize": "8",
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"SSAArgs": "7"
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},
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"LoadMem": {
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"HasDest": true,
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"DestSize": "Size",
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"SSAArgs": "1",
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"Args": [
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"uint8_t", "Size"
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]
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},
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"StoreMem": {
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"SSAArgs": "2",
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"Args": [
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"uint8_t", "Size"
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]
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},
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"Add": {
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"HasDest": true,
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"Dispatcher": true,
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"SSAArgs": "2"
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},
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"Sub": {
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"HasDest": true,
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"Dispatcher": true,
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"SSAArgs": "2"
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},
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"Mul": {
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"HasDest": true,
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"Dispatcher": true,
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"SSAArgs": "2"
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},
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"UMul": {
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"HasDest": true,
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"Dispatcher": true,
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"SSAArgs": "2"
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},
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"Div": {
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"HasDest": true,
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"Dispatcher": true,
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"SSAArgs": "2"
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},
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"UDiv": {
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"HasDest": true,
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"Dispatcher": true,
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"SSAArgs": "2"
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},
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"Rem": {
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"HasDest": true,
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"Dispatcher": true,
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"SSAArgs": "2"
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},
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"URem": {
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"HasDest": true,
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"Dispatcher": true,
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"SSAArgs": "2"
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},
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"MulH": {
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"HasDest": true,
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"Dispatcher": true,
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"SSAArgs": "2"
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},
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"UMulH": {
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"HasDest": true,
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"Dispatcher": true,
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"SSAArgs": "2"
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},
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"Or": {
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"HasDest": true,
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"Dispatcher": true,
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"SSAArgs": "2"
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},
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"And": {
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"HasDest": true,
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"Dispatcher": true,
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"SSAArgs": "2"
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},
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"Xor": {
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"HasDest": true,
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"Dispatcher": true,
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"SSAArgs": "2"
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},
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"Lshl": {
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"HasDest": true,
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"Dispatcher": true,
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"SSAArgs": "2"
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},
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"Lshr": {
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"HasDest": true,
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"Dispatcher": true,
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"SSAArgs": "2"
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},
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"Ashr": {
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"HasDest": true,
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"Dispatcher": true,
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"SSAArgs": "2"
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},
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"Rol": {
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"HasDest": true,
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"Dispatcher": true,
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"SSAArgs": "2"
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},
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"Ror": {
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"HasDest": true,
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"Dispatcher": true,
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"SSAArgs": "2"
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},
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"LDiv": {
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"HasDest": true,
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"SSAArgs": "3"
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},
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"LUDiv": {
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"HasDest": true,
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"SSAArgs": "3"
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},
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"LRem": {
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"HasDest": true,
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"SSAArgs": "3"
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},
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"LURem": {
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"HasDest": true,
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"SSAArgs": "3"
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},
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"Zext": {
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"HasDest": true,
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"DestSize": "SrcSize / 4",
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"SSAArgs": "1",
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"Args": [
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"uint8_t", "SrcSize"
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]
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},
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"Sext": {
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"HasDest": true,
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"DestSize": "SrcSize / 4",
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"SSAArgs": "1",
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"Args": [
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"uint8_t", "SrcSize"
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]
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},
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"Neg": {
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"HasDest": true,
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"DispatcherUnary": true,
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"SSAArgs": "1"
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},
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"Popcount": {
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"HasDest": true,
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"DispatcherUnary": true,
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"SSAArgs": "1"
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},
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"FindLSB": {
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"HasDest": true,
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"DispatcherUnary": true,
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"SSAArgs": "1"
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},
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"FindMSB": {
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"HasDest": true,
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"DispatcherUnary": true,
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"SSAArgs": "1"
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},
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"Rev": {
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"HasDest": true,
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"DispatcherUnary": true,
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"SSAArgs": "1"
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},
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"CPUID": {
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"HasDest": true,
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"FixedDestSize": "4",
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"NumElements": "4",
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"SSAArgs": "1"
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},
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"Bfi": {
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"HasDest": true,
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"DestSize": "GetOpSize(ssa0)",
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"SSAArgs": "2",
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"Args": [
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"uint8_t", "Width",
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"uint8_t", "lsb"
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]
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},
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"Bfe": {
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"HasDest": true,
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"DestSize": "GetOpSize(ssa0)",
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"SSAArgs": "1",
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"Args": [
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"uint8_t", "Width",
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"uint8_t", "lsb"
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]
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},
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"Sbfe": {
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"HasDest": true,
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"SSAArgs": "1",
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"Args": [
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"uint8_t", "Width",
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"uint8_t", "lsb"
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]
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},
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"Select": {
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"HasDest": true,
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"SSAArgs": "4",
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"Args": [
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"uint8_t", "Cond"
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]
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},
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"CAS": {
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"HasDest": true,
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"DestSize": "GetOpSize(ssa0)",
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"SSAArgs": "3"
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},
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"Print": {
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"DispatcherUnary": true,
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"SSAArgs": "1"
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},
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"CreateVector2": {
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"HasDest": true,
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"DestSize": "GetOpSize(ssa0) * 2",
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"SSAArgs": "2"
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},
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"CreateVector3": {
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"HasDest": true,
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"DestSize": "GetOpSize(ssa0) * 3",
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"SSAArgs": "3"
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},
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"CreateVector4": {
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"HasDest": true,
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"DestSize": "GetOpSize(ssa0) * 4",
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"SSAArgs": "4"
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},
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"SplatVector2": {
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"HasDest": true,
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"NumElements": "2",
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"DestSize": "GetOpSize(ssa0) * 2",
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"SSAArgs": "1"
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},
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"SplatVector3": {
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"HasDest": true,
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"NumElements": "3",
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"DestSize": "GetOpSize(ssa0) * 3",
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"SSAArgs": "1"
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},
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"SplatVector4": {
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"HasDest": true,
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"NumElements": "4",
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"DestSize": "GetOpSize(ssa0) * 4",
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"SSAArgs": "1"
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},
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"ExtractElement": {
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"HasDest": true,
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"DestSize": "GetOpSize(ssa0)",
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"SSAArgs": "1",
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"Args": [
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"uint8_t", "Idx"
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]
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},
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"VOr": {
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"HasDest": true,
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"Dispatcher": true,
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"SSAArgs": "2"
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},
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"VXor": {
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"HasDest": true,
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"Dispatcher": true,
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"SSAArgs": "2"
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},
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"VAdd": {
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"HasDest": true,
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"SSAArgs": "2",
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"Args": [
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"uint8_t", "RegisterSize",
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"uint8_t", "ElementSize"
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]
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},
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"VSub": {
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"HasDest": true,
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"SSAArgs": "2",
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"Args": [
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"uint8_t", "RegisterSize",
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"uint8_t", "ElementSize"
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]
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},
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"VUMin": {
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"HasDest": true,
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"SSAArgs": "2",
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"Args": [
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"uint8_t", "RegisterSize",
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"uint8_t", "ElementSize"
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]
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},
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"VSMin": {
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"HasDest": true,
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"SSAArgs": "2",
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"Args": [
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"uint8_t", "RegisterSize",
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"uint8_t", "ElementSize"
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]
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},
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"VZip": {
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"HasDest": true,
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"SSAArgs": "2",
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"Args": [
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"uint8_t", "RegisterSize",
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"uint8_t", "ElementSize"
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]
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},
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"VZip2": {
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"HasDest": true,
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"SSAArgs": "2",
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"Args": [
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"uint8_t", "RegisterSize",
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"uint8_t", "ElementSize"
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]
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},
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"VCMPEQ": {
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"HasDest": true,
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"SSAArgs": "2",
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"Args": [
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"uint8_t", "RegisterSize",
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"uint8_t", "ElementSize"
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]
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},
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"VCMPGT": {
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"HasDest": true,
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"SSAArgs": "2",
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"Args": [
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"uint8_t", "RegisterSize",
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"uint8_t", "ElementSize"
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]
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},
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"VUShl": {
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"HasDest": true,
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"SSAArgs": "2",
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"Args": [
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"uint8_t", "RegisterSize",
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"uint8_t", "ElementSize"
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]
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},
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"VUShlS": {
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"HasDest": true,
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"SSAArgs": "2",
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"Args": [
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"uint8_t", "RegisterSize",
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"uint8_t", "ElementSize"
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]
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},
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"VUShr": {
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"HasDest": true,
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"SSAArgs": "2",
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"Args": [
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"uint8_t", "RegisterSize",
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"uint8_t", "ElementSize"
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]
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},
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"VInsElement": {
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"HasDest": true,
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"SSAArgs": "2",
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"Args": [
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"uint8_t", "RegisterSize",
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"uint8_t", "ElementSize",
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"uint8_t", "DestIdx",
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"uint8_t", "SrcIdx"
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]
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},
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"VExtr": {
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"HasDest": true,
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"SSAArgs": "2",
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"Args": [
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"uint8_t", "RegisterSize",
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"uint8_t", "ElementSize",
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"uint8_t", "Index"
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]
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},
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"Last": {
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"Last": true,
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"Args": []
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}
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}
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}
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