mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 23:00:17 +02:00
Ryan Houdek
0fbf403787
Necessary for asm tests to still run in the host "core". Useful for ensuring correct behaviour of our assembly tests.
327 lines
12 KiB
C++
327 lines
12 KiB
C++
// SPDX-License-Identifier: MIT
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#include "Interface/Core/CPUID.h"
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#include <FEXCore/Core/HostFeatures.h>
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#include "aarch64/assembler-aarch64.h"
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#include "aarch64/cpu-aarch64.h"
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#include "aarch64/disasm-aarch64.h"
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#include "aarch64/assembler-aarch64.h"
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#ifdef _M_X86_64
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#define XBYAK64
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#define XBYAK_CUSTOM_ALLOC
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#define XBYAK_CUSTOM_MALLOC FEXCore::Allocator::malloc
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#define XBYAK_CUSTOM_FREE FEXCore::Allocator::free
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#define XBYAK_CUSTOM_SETS
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#define XBYAK_STD_UNORDERED_SET fextl::unordered_set
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#define XBYAK_STD_UNORDERED_MAP fextl::unordered_map
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#define XBYAK_STD_UNORDERED_MULTIMAP fextl::unordered_multimap
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#define XBYAK_STD_LIST fextl::list
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#define XBYAK_NO_EXCEPTION
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#include <FEXCore/fextl/list.h>
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#include <FEXCore/fextl/unordered_map.h>
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#include <FEXCore/fextl/unordered_set.h>
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#include <xbyak/xbyak.h>
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#include <xbyak/xbyak_util.h>
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#endif
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namespace FEXCore {
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// Data Zero Prohibited flag
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// 0b0 = ZVA/GVA/GZVA permitted
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// 0b1 = ZVA/GVA/GZVA prohibited
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[[maybe_unused]] constexpr uint32_t DCZID_DZP_MASK = 0b1'0000;
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// Log2 of the blocksize in 32-bit words
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[[maybe_unused]] constexpr uint32_t DCZID_BS_MASK = 0b0'1111;
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#ifdef _M_ARM_64
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[[maybe_unused]] static uint32_t GetDCZID() {
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uint64_t Result{};
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__asm("mrs %[Res], DCZID_EL0"
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: [Res] "=r" (Result));
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return Result;
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}
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static uint32_t GetFPCR() {
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uint64_t Result{};
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__asm ("mrs %[Res], FPCR"
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: [Res] "=r" (Result));
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return Result;
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}
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static void SetFPCR(uint64_t Value) {
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__asm ("msr FPCR, %[Value]"
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:: [Value] "r" (Value));
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}
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#else
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static uint32_t GetDCZID() {
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// Return unsupported
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return DCZID_DZP_MASK;
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}
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#endif
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static void OverrideFeatures(HostFeatures *Features) {
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// Override features if the user has specifically called for it.
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FEX_CONFIG_OPT(HostFeatures, HOSTFEATURES);
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if (!HostFeatures()) {
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// Early exit if no features are overriden.
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return;
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}
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const bool DisableAVX = HostFeatures() & FEXCore::Config::HostFeatures::DISABLEAVX;
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const bool EnableAVX = HostFeatures() & FEXCore::Config::HostFeatures::ENABLEAVX;
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LogMan::Throw::AFmt(!(DisableAVX && EnableAVX), "Disabling and Enabling CPU features are mutually exclusive");
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const bool DisableSVE = HostFeatures() & FEXCore::Config::HostFeatures::DISABLESVE;
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const bool EnableSVE = HostFeatures() & FEXCore::Config::HostFeatures::ENABLESVE;
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LogMan::Throw::AFmt(!(DisableSVE && EnableSVE), "Disabling and Enabling CPU features are mutually exclusive");
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const bool DisableAFP = HostFeatures() & FEXCore::Config::HostFeatures::DISABLEAFP;
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const bool EnableAFP = HostFeatures() & FEXCore::Config::HostFeatures::ENABLEAFP;
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LogMan::Throw::AFmt(!(DisableAFP && EnableAFP), "Disabling and Enabling CPU features are mutually exclusive");
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const bool DisableLRCPC = HostFeatures() & FEXCore::Config::HostFeatures::DISABLELRCPC;
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const bool EnableLRCPC = HostFeatures() & FEXCore::Config::HostFeatures::ENABLELRCPC;
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LogMan::Throw::AFmt(!(DisableLRCPC && EnableLRCPC), "Disabling and Enabling CPU features are mutually exclusive");
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const bool DisableLRCPC2 = HostFeatures() & FEXCore::Config::HostFeatures::DISABLELRCPC2;
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const bool EnableLRCPC2 = HostFeatures() & FEXCore::Config::HostFeatures::ENABLELRCPC2;
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LogMan::Throw::AFmt(!(DisableLRCPC2 && EnableLRCPC2), "Disabling and Enabling CPU features are mutually exclusive");
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const bool DisableCSSC = HostFeatures() & FEXCore::Config::HostFeatures::DISABLECSSC;
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const bool EnableCSSC = HostFeatures() & FEXCore::Config::HostFeatures::ENABLECSSC;
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LogMan::Throw::AFmt(!(DisableCSSC && EnableCSSC), "Disabling and Enabling CPU features are mutually exclusive");
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const bool DisablePMULL128 = HostFeatures() & FEXCore::Config::HostFeatures::DISABLEPMULL128;
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const bool EnablePMULL128 = HostFeatures() & FEXCore::Config::HostFeatures::ENABLEPMULL128;
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LogMan::Throw::AFmt(!(DisablePMULL128 && EnablePMULL128), "Disabling and Enabling CPU features are mutually exclusive");
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const bool DisableRNG = HostFeatures() & FEXCore::Config::HostFeatures::DISABLERNG;
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const bool EnableRNG = HostFeatures() & FEXCore::Config::HostFeatures::ENABLERNG;
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LogMan::Throw::AFmt(!(DisableRNG && EnableRNG), "Disabling and Enabling CPU features are mutually exclusive");
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const bool DisableCLZERO = HostFeatures() & FEXCore::Config::HostFeatures::DISABLECLZERO;
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const bool EnableCLZERO = HostFeatures() & FEXCore::Config::HostFeatures::ENABLECLZERO;
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LogMan::Throw::AFmt(!(DisableCLZERO && EnableCLZERO), "Disabling and Enabling CPU features are mutually exclusive");
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const bool DisableAtomics = HostFeatures() & FEXCore::Config::HostFeatures::DISABLEATOMICS;
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const bool EnableAtomics = HostFeatures() & FEXCore::Config::HostFeatures::ENABLEATOMICS;
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LogMan::Throw::AFmt(!(DisableAtomics && EnableAtomics), "Disabling and Enabling CPU features are mutually exclusive");
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const bool DisableFCMA = HostFeatures() & FEXCore::Config::HostFeatures::DISABLEFCMA;
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const bool EnableFCMA = HostFeatures() & FEXCore::Config::HostFeatures::ENABLEFCMA;
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LogMan::Throw::AFmt(!(DisableFCMA && EnableFCMA), "Disabling and Enabling CPU features are mutually exclusive");
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const bool DisableFlagM = HostFeatures() & FEXCore::Config::HostFeatures::DISABLEFLAGM;
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const bool EnableFlagM = HostFeatures() & FEXCore::Config::HostFeatures::ENABLEFLAGM;
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LogMan::Throw::AFmt(!(DisableFlagM && EnableFlagM), "Disabling and Enabling CPU features are mutually exclusive");
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const bool DisableFlagM2 = HostFeatures() & FEXCore::Config::HostFeatures::DISABLEFLAGM2;
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const bool EnableFlagM2 = HostFeatures() & FEXCore::Config::HostFeatures::ENABLEFLAGM2;
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LogMan::Throw::AFmt(!(DisableFlagM2 && EnableFlagM2), "Disabling and Enabling CPU features are mutually exclusive");
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if (EnableAVX) {
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Features->SupportsAVX = true;
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}
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else if (DisableAVX) {
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Features->SupportsAVX = false;
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}
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if (EnableSVE) {
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Features->SupportsSVE = true;
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}
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else if (DisableSVE) {
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Features->SupportsSVE = false;
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}
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if (EnableAFP) {
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Features->SupportsFlushInputsToZero = true;
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}
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else if (DisableAFP) {
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Features->SupportsFlushInputsToZero = false;
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}
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if (EnableLRCPC) {
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Features->SupportsRCPC = true;
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}
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else if (DisableLRCPC) {
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Features->SupportsRCPC = false;
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}
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if (EnableLRCPC2) {
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Features->SupportsTSOImm9 = true;
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}
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else if (DisableLRCPC2) {
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Features->SupportsTSOImm9 = false;
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}
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if (EnableCSSC) {
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Features->SupportsCSSC = true;
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}
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else if (DisableCSSC) {
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Features->SupportsCSSC = false;
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}
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if (EnablePMULL128) {
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Features->SupportsPMULL_128Bit = true;
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}
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else if (DisablePMULL128) {
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Features->SupportsPMULL_128Bit = false;
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}
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if (EnableRNG) {
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Features->SupportsRAND = true;
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}
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else if (DisableRNG) {
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Features->SupportsRAND = false;
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}
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if (EnableCLZERO) {
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Features->SupportsCLZERO = true;
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}
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else if (DisableCLZERO) {
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Features->SupportsCLZERO = false;
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}
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if (EnableAtomics) {
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Features->SupportsAtomics = true;
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}
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else if (DisableAtomics) {
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Features->SupportsAtomics = false;
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}
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if (EnableFCMA) {
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Features->SupportsFCMA = true;
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}
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else if (DisableFCMA) {
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Features->SupportsFCMA = false;
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}
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if (EnableFlagM) {
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Features->SupportsFlagM = true;
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}
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else if (DisableFlagM) {
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Features->SupportsFlagM = false;
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}
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if (EnableFlagM2) {
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Features->SupportsFlagM2 = true;
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}
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else if (DisableFlagM2) {
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Features->SupportsFlagM2 = false;
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}
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}
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HostFeatures::HostFeatures() {
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#ifdef VIXL_SIMULATOR
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auto Features = vixl::CPUFeatures::All();
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#elif !defined(_WIN32)
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auto Features = vixl::CPUFeatures::InferFromOS();
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#else
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// Need to use ID registers in WINE.
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auto Features = vixl::CPUFeatures::InferFromIDRegisters();
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#endif
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SupportsAES = Features.Has(vixl::CPUFeatures::Feature::kAES);
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SupportsCRC = Features.Has(vixl::CPUFeatures::Feature::kCRC32);
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SupportsAtomics = Features.Has(vixl::CPUFeatures::Feature::kAtomics);
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SupportsRAND = Features.Has(vixl::CPUFeatures::Feature::kRNG);
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// Only supported when FEAT_AFP is supported
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SupportsFlushInputsToZero = Features.Has(vixl::CPUFeatures::Feature::kAFP);
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SupportsRCPC = Features.Has(vixl::CPUFeatures::Feature::kRCpc);
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SupportsTSOImm9 = Features.Has(vixl::CPUFeatures::Feature::kRCpcImm);
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SupportsPMULL_128Bit = Features.Has(vixl::CPUFeatures::Feature::kPmull1Q);
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SupportsCSSC = Features.Has(vixl::CPUFeatures::Feature::kCSSC);
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SupportsFCMA = Features.Has(vixl::CPUFeatures::Feature::kFcma);
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SupportsFlagM = Features.Has(vixl::CPUFeatures::Feature::kFlagM);
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SupportsFlagM2 = Features.Has(vixl::CPUFeatures::Feature::kAXFlag);
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Supports3DNow = true;
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SupportsSSE4A = true;
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#ifdef VIXL_SIMULATOR
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// Hardcode enable SVE with 256-bit wide registers.
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SupportsSVE = true;
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SupportsAVX = true;
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#else
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SupportsSVE = Features.Has(vixl::CPUFeatures::Feature::kSVE);
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SupportsAVX = Features.Has(vixl::CPUFeatures::Feature::kSVE2) &&
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vixl::aarch64::CPU::ReadSVEVectorLengthInBits() >= 256;
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#endif
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SupportsSHA = true;
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SupportsBMI1 = true;
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SupportsBMI2 = true;
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SupportsCLWB = true;
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if (!SupportsAtomics) {
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WARN_ONCE_FMT("Host CPU doesn't support atomics. Expect bad performance");
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}
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#ifdef _M_ARM_64
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// We need to get the CPU's cache line size
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// We expect sane targets that have correct cacheline sizes across clusters
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uint64_t CTR;
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__asm volatile ("mrs %[ctr], ctr_el0"
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: [ctr] "=r"(CTR));
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DCacheLineSize = 4 << ((CTR >> 16) & 0xF);
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ICacheLineSize = 4 << (CTR & 0xF);
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// Test if this CPU supports float exception trapping by attempting to enable
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// On unsupported these bits are architecturally defined as RAZ/WI
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constexpr uint32_t ExceptionEnableTraps =
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(1U << 8) | // Invalid Operation float exception trap enable
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(1U << 9) | // Divide by zero float exception trap enable
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(1U << 10) | // Overflow float exception trap enable
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(1U << 11) | // Underflow float exception trap enable
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(1U << 12) | // Inexact float exception trap enable
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(1U << 15); // Input Denormal float exception trap enable
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uint32_t OriginalFPCR = GetFPCR();
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uint32_t FPCR = OriginalFPCR | ExceptionEnableTraps;
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SetFPCR(FPCR);
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FPCR = GetFPCR();
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SupportsFloatExceptions = (FPCR & ExceptionEnableTraps) == ExceptionEnableTraps;
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// Set FPCR back to original just in case anything changed
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SetFPCR(OriginalFPCR);
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#endif
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#ifdef VIXL_SIMULATOR
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// simulator doesn't support dc(ZVA)
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SupportsCLZERO = false;
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#else
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// Check if we can support cacheline clears
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uint32_t DCZID = GetDCZID();
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if ((DCZID & DCZID_DZP_MASK) == 0) {
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uint32_t DCZID_Log2 = DCZID & DCZID_BS_MASK;
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uint32_t DCZID_Bytes = (1 << DCZID_Log2) * sizeof(uint32_t);
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// If the DC ZVA size matches the emulated cache line size
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// This means we can use the instruction
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SupportsCLZERO = DCZID_Bytes == CPUIDEmu::CACHELINE_SIZE;
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}
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#endif
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#if defined(_M_X86_64) && !defined(VIXL_SIMULATOR)
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Xbyak::util::Cpu X86Features{};
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SupportsAES = X86Features.has(Xbyak::util::Cpu::tAESNI);
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SupportsCRC = X86Features.has(Xbyak::util::Cpu::tSSE42);
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SupportsRAND = X86Features.has(Xbyak::util::Cpu::tRDRAND) && X86Features.has(Xbyak::util::Cpu::tRDSEED);
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SupportsRCPC = true;
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SupportsTSOImm9 = true;
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Supports3DNow = X86Features.has(Xbyak::util::Cpu::t3DN) && X86Features.has(Xbyak::util::Cpu::tE3DN);
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SupportsSSE4A = X86Features.has(Xbyak::util::Cpu::tSSE4a);
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SupportsAVX = true;
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SupportsSHA = X86Features.has(Xbyak::util::Cpu::tSHA);
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SupportsBMI1 = X86Features.has(Xbyak::util::Cpu::tBMI1);
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SupportsBMI2 = X86Features.has(Xbyak::util::Cpu::tBMI2);
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SupportsCLWB = X86Features.has(Xbyak::util::Cpu::tCLWB);
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SupportsPMULL_128Bit = X86Features.has(Xbyak::util::Cpu::tPCLMULQDQ);
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// xbyak doesn't know how to check for CLZero
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// First ensure we support a new enough extended CPUID function range
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uint32_t data[4];
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Xbyak::util::Cpu::getCpuid(0x8000'0000, data);
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if (data[0] >= 0x8000'0008U) {
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// CLZero defined in 8000_00008_EBX[bit 0]
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Xbyak::util::Cpu::getCpuid(0x8000'0008, data);
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SupportsCLZERO = data[1] & 1;
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}
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SupportsFlushInputsToZero = true;
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SupportsFloatExceptions = true;
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#endif
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OverrideFeatures(this);
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}
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}
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