Alyssa Rosenzweig 01fcca884b OpcodeDispatcher: Optimize rotates ...

In the non-immediate cases, we can amortize some work between the two
flags to come out 1 instruction ahead.

In the immediate case, costs us an extra 2 instructions compared to
before we packed NZCV flags, but this mitigates a bigger instr count
regression that this PR would otherwise have. Coming out ahead will
require FlagM and smarter RA, but is doable.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2023-08-02 16:54:56 -04:00

..

Config

FEXCore: Remove erroneous asserts in the project

2023-07-28 13:36:05 -07:00

Context

Context: Make BackendFeatures public

2023-08-02 12:38:00 -04:00

Core

OpcodeDispatcher: Optimize rotates

2023-08-02 16:54:56 -04:00

GDBJIT

SourcecodeResolver: Convert string to fextl

2023-03-16 03:21:45 -07:00

HLE/Thunks

Thunks: Mostly reverts #2672

2023-05-18 15:50:55 -07:00

IR

IR: Add TEST opcode

2023-08-02 12:38:00 -04:00