{
  "Features": {
    "Bitness": 64,
    "EnabledHostFeatures": [
      "CLZERO"
    ],
    "DisabledHostFeatures": [
      "SVE128",
      "SVE256",
      "AFP",
      "FLAGM",
      "FLAGM2"
    ]
  },
  "Instructions": {
    "xgetbv": {
      "ExpectedInstructionCount": 54,
      "Comment": "0xF 0x01 /2 RM-0",
      "ExpectedArm64ASM": [
        "sub sp, sp, #0xf0 (240)",
        "mov x3, sp",
        "st1 {v2.2d, v3.2d}, [x3], #32",
        "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x3], #64",
        "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x3], #64",
        "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x3], #64",
        "str x30, [x3]",
        "mrs x3, nzcv",
        "str w3, [x28, #1000]",
        "stp x4, x5, [x28, #280]",
        "stp x6, x7, [x28, #296]",
        "stp x8, x9, [x28, #312]",
        "stp x10, x11, [x28, #328]",
        "stp x12, x13, [x28, #344]",
        "stp x14, x15, [x28, #360]",
        "stp x16, x17, [x28, #376]",
        "stp x19, x29, [x28, #392]",
        "str x26, [x28, #1024]",
        "str x27, [x28, #1032]",
        "add x3, x28, #0x1a0 (416)",
        "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x3], #64",
        "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x3], #64",
        "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x3], #64",
        "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x3], #64",
        "mov w1, w5",
        "ldr x0, [x28, #1368]",
        "ldr x2, [x28, #1384]",
        "blr x2",
        "ldr w4, [x28, #1000]",
        "msr nzcv, x4",
        "add x4, x28, #0x1a0 (416)",
        "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
        "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
        "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
        "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
        "ldp x4, x5, [x28, #280]",
        "ldp x6, x7, [x28, #296]",
        "ldp x8, x9, [x28, #312]",
        "ldp x10, x11, [x28, #328]",
        "ldp x12, x13, [x28, #344]",
        "ldp x14, x15, [x28, #360]",
        "ldp x16, x17, [x28, #376]",
        "ldp x19, x29, [x28, #392]",
        "ldr x26, [x28, #1024]",
        "ldr x27, [x28, #1032]",
        "ld1 {v2.2d, v3.2d}, [sp], #32",
        "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
        "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
        "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
        "ldr x30, [sp], #16",
        "mov w20, w0",
        "lsr x21, x0, #32",
        "mov w6, w21",
        "mov w4, w20"
      ]
    },
    "rdtscp": {
      "ExpectedInstructionCount": 21,
      "Comment": "0xF 0x01 /7 RM-1",
      "ExpectedArm64ASM": [
        "dmb ld",
        "mrs x20, S3_3_c14_c0_2",
        "lsl w4, w20, #7",
        "lsr x6, x20, #25",
        "mrs x0, nzcv",
        "str w0, [x28, #1000]",
        "str x8, [x28, #312]",
        "mov w0, #0x100",
        "str x0, [x28, #1312]",
        "sub sp, sp, #0x10 (16)",
        "mov w8, #0xa8",
        "mov x0, sp",
        "add x1, sp, #0x4 (4)",
        "svc #0x0",
        "ldp w0, w1, [sp]",
        "sub sp, sp, #0x10 (16)",
        "ldr w8, [x28, #1000]",
        "msr nzcv, x8",
        "ldr x8, [x28, #312]",
        "str xzr, [x28, #1312]",
        "orr x5, x0, x1, lsl #12"
      ]
    },
    "clzero rax": {
      "ExpectedInstructionCount": 1,
      "Comment": "0xF 0x01 /7 RM-4",
      "ExpectedArm64ASM": [
        "dc zva, x4"
      ]
    }
  }
}