{
  "Features": {
    "Bitness": 64,
    "EnabledHostFeatures": [
      "MOPS"
    ],
    "DisabledHostFeatures": [
      "SVE128",
      "SVE256",
      "AFP",
      "FLAGM",
      "FLAGM2"
    ],
    "BinaryCacheVersion": 13
  },
  "Instructions": {
    "rep movsb": {
      "ExpectedInstructionCount": 109,
      "Comment": "0xa4",
      "ExpectedArm64ASM": [
        "ldrsb x22, [x28, #1018]",
        "mov x0, x7",
        "mov x1, x11",
        "mov x2, x10",
        "tbnz w22, #1, #+0xc0",
        "cbz x0, #+0xa4",
        "mrs x3, nzcv",
        "sub x0, x1, x2",
        "cmp x0, x7",
        "mov x0, x7",
        "bc.lt #+0x18",
        "cpyfp [x1]!, [x2]!, x0!",
        "cpyfm [x1]!, [x2]!, x0!",
        "cpyfe [x1]!, [x2]!, x0!",
        "msr nzcv, x3",
        "b #+0x7c",
        "msr nzcv, x3",
        "sub x3, x1, x2",
        "tbz x3, #63, #+0x8",
        "neg x3, x3",
        "sub x3, x3, #0x20 (32)",
        "tbnz x3, #63, #+0x54",
        "sub x0, x0, #0x20 (32)",
        "tbnz x0, #63, #+0x44",
        "sub x0, x0, #0x20 (32)",
        "tbnz x0, #63, #+0x1c",
        "ldp q0, q1, [x2], #32",
        "stp q0, q1, [x1], #32",
        "ldp q0, q1, [x2], #32",
        "stp q0, q1, [x1], #32",
        "sub x0, x0, #0x40 (64)",
        "tbz x0, #63, #-0x14",
        "add x0, x0, #0x40 (64)",
        "cbz x0, #+0x34",
        "sub x0, x0, #0x20 (32)",
        "tbnz x0, #63, #+0x14",
        "ldp q0, q1, [x2], #32",
        "stp q0, q1, [x1], #32",
        "sub x0, x0, #0x20 (32)",
        "tbz x0, #63, #-0xc",
        "add x0, x0, #0x20 (32)",
        "cbz x0, #+0x14",
        "ldrb w3, [x2], #1",
        "strb w3, [x1], #1",
        "sub x0, x0, #0x1 (1)",
        "cbnz x0, #-0xc",
        "mov x0, x11",
        "mov x1, x10",
        "mov x2, x7",
        "add x21, x0, x2",
        "add x20, x1, x2",
        "b #+0xdc",
        "cbz x0, #+0xc4",
        "mrs x3, nzcv",
        "sub x0, x1, x2",
        "cmp x0, x7",
        "mov x0, x7",
        "bc.lt #+0x28",
        "sub x1, x1, x0",
        "sub x2, x2, x0",
        "add x1, x1, #0x1 (1)",
        "add x2, x2, #0x1 (1)",
        "cpyfp [x1]!, [x2]!, x0!",
        "cpyfm [x1]!, [x2]!, x0!",
        "cpyfe [x1]!, [x2]!, x0!",
        "msr nzcv, x3",
        "b #+0x8c",
        "msr nzcv, x3",
        "sub x3, x1, x2",
        "tbz x3, #63, #+0x8",
        "neg x3, x3",
        "sub x3, x3, #0x20 (32)",
        "tbnz x3, #63, #+0x64",
        "sub x1, x1, #0x1f (31)",
        "sub x2, x2, #0x1f (31)",
        "sub x0, x0, #0x20 (32)",
        "tbnz x0, #63, #+0x44",
        "sub x0, x0, #0x20 (32)",
        "tbnz x0, #63, #+0x1c",
        "ldp q0, q1, [x2], #-32",
        "stp q0, q1, [x1], #-32",
        "ldp q0, q1, [x2], #-32",
        "stp q0, q1, [x1], #-32",
        "sub x0, x0, #0x40 (64)",
        "tbz x0, #63, #-0x14",
        "add x0, x0, #0x40 (64)",
        "cbz x0, #+0x3c",
        "sub x0, x0, #0x20 (32)",
        "tbnz x0, #63, #+0x14",
        "ldp q0, q1, [x2], #-32",
        "stp q0, q1, [x1], #-32",
        "sub x0, x0, #0x20 (32)",
        "tbz x0, #63, #-0xc",
        "add x0, x0, #0x20 (32)",
        "cbz x0, #+0x1c",
        "add x1, x1, #0x1f (31)",
        "add x2, x2, #0x1f (31)",
        "ldrb w3, [x2], #-1",
        "strb w3, [x1], #-1",
        "sub x0, x0, #0x1 (1)",
        "cbnz x0, #-0xc",
        "mov x0, x11",
        "mov x1, x10",
        "mov x2, x7",
        "sub x21, x0, x2",
        "sub x20, x1, x2",
        "mov w7, #0x0",
        "mov x11, x21",
        "mov x10, x20"
      ]
    },
    "rep movsw": {
      "ExpectedInstructionCount": 111,
      "Comment": "0xa5",
      "ExpectedArm64ASM": [
        "ldrsb x22, [x28, #1018]",
        "mov x0, x7",
        "mov x1, x11",
        "mov x2, x10",
        "tbnz w22, #1, #+0xc4",
        "cbz x0, #+0xa8",
        "mrs x3, nzcv",
        "sub x0, x1, x2",
        "cmp x0, x7",
        "mov x0, x7",
        "bc.lt #+0x1c",
        "lsl x0, x0, #1",
        "cpyfp [x1]!, [x2]!, x0!",
        "cpyfm [x1]!, [x2]!, x0!",
        "cpyfe [x1]!, [x2]!, x0!",
        "msr nzcv, x3",
        "b #+0x7c",
        "msr nzcv, x3",
        "sub x3, x1, x2",
        "tbz x3, #63, #+0x8",
        "neg x3, x3",
        "sub x3, x3, #0x20 (32)",
        "tbnz x3, #63, #+0x54",
        "sub x0, x0, #0x10 (16)",
        "tbnz x0, #63, #+0x44",
        "sub x0, x0, #0x10 (16)",
        "tbnz x0, #63, #+0x1c",
        "ldp q0, q1, [x2], #32",
        "stp q0, q1, [x1], #32",
        "ldp q0, q1, [x2], #32",
        "stp q0, q1, [x1], #32",
        "sub x0, x0, #0x20 (32)",
        "tbz x0, #63, #-0x14",
        "add x0, x0, #0x20 (32)",
        "cbz x0, #+0x34",
        "sub x0, x0, #0x10 (16)",
        "tbnz x0, #63, #+0x14",
        "ldp q0, q1, [x2], #32",
        "stp q0, q1, [x1], #32",
        "sub x0, x0, #0x10 (16)",
        "tbz x0, #63, #-0xc",
        "add x0, x0, #0x10 (16)",
        "cbz x0, #+0x14",
        "ldrh w3, [x2], #2",
        "strh w3, [x1], #2",
        "sub x0, x0, #0x1 (1)",
        "cbnz x0, #-0xc",
        "mov x0, x11",
        "mov x1, x10",
        "mov x2, x7",
        "add x21, x0, x2, lsl #1",
        "add x20, x1, x2, lsl #1",
        "b #+0xe0",
        "cbz x0, #+0xc8",
        "mrs x3, nzcv",
        "sub x0, x1, x2",
        "cmp x0, x7",
        "mov x0, x7",
        "bc.lt #+0x2c",
        "lsl x0, x0, #1",
        "sub x1, x1, x0",
        "sub x2, x2, x0",
        "add x1, x1, #0x2 (2)",
        "add x2, x2, #0x2 (2)",
        "cpyfp [x1]!, [x2]!, x0!",
        "cpyfm [x1]!, [x2]!, x0!",
        "cpyfe [x1]!, [x2]!, x0!",
        "msr nzcv, x3",
        "b #+0x8c",
        "msr nzcv, x3",
        "sub x3, x1, x2",
        "tbz x3, #63, #+0x8",
        "neg x3, x3",
        "sub x3, x3, #0x20 (32)",
        "tbnz x3, #63, #+0x64",
        "sub x1, x1, #0x1e (30)",
        "sub x2, x2, #0x1e (30)",
        "sub x0, x0, #0x10 (16)",
        "tbnz x0, #63, #+0x44",
        "sub x0, x0, #0x10 (16)",
        "tbnz x0, #63, #+0x1c",
        "ldp q0, q1, [x2], #-32",
        "stp q0, q1, [x1], #-32",
        "ldp q0, q1, [x2], #-32",
        "stp q0, q1, [x1], #-32",
        "sub x0, x0, #0x20 (32)",
        "tbz x0, #63, #-0x14",
        "add x0, x0, #0x20 (32)",
        "cbz x0, #+0x3c",
        "sub x0, x0, #0x10 (16)",
        "tbnz x0, #63, #+0x14",
        "ldp q0, q1, [x2], #-32",
        "stp q0, q1, [x1], #-32",
        "sub x0, x0, #0x10 (16)",
        "tbz x0, #63, #-0xc",
        "add x0, x0, #0x10 (16)",
        "cbz x0, #+0x1c",
        "add x1, x1, #0x1e (30)",
        "add x2, x2, #0x1e (30)",
        "ldrh w3, [x2], #-2",
        "strh w3, [x1], #-2",
        "sub x0, x0, #0x1 (1)",
        "cbnz x0, #-0xc",
        "mov x0, x11",
        "mov x1, x10",
        "mov x2, x7",
        "sub x21, x0, x2, lsl #1",
        "sub x20, x1, x2, lsl #1",
        "mov w7, #0x0",
        "mov x11, x21",
        "mov x10, x20"
      ]
    },
    "rep movsd": {
      "ExpectedInstructionCount": 111,
      "Comment": "0xa5",
      "ExpectedArm64ASM": [
        "ldrsb x22, [x28, #1018]",
        "mov x0, x7",
        "mov x1, x11",
        "mov x2, x10",
        "tbnz w22, #1, #+0xc4",
        "cbz x0, #+0xa8",
        "mrs x3, nzcv",
        "sub x0, x1, x2",
        "cmp x0, x7",
        "mov x0, x7",
        "bc.lt #+0x1c",
        "lsl x0, x0, #2",
        "cpyfp [x1]!, [x2]!, x0!",
        "cpyfm [x1]!, [x2]!, x0!",
        "cpyfe [x1]!, [x2]!, x0!",
        "msr nzcv, x3",
        "b #+0x7c",
        "msr nzcv, x3",
        "sub x3, x1, x2",
        "tbz x3, #63, #+0x8",
        "neg x3, x3",
        "sub x3, x3, #0x20 (32)",
        "tbnz x3, #63, #+0x54",
        "sub x0, x0, #0x8 (8)",
        "tbnz x0, #63, #+0x44",
        "sub x0, x0, #0x8 (8)",
        "tbnz x0, #63, #+0x1c",
        "ldp q0, q1, [x2], #32",
        "stp q0, q1, [x1], #32",
        "ldp q0, q1, [x2], #32",
        "stp q0, q1, [x1], #32",
        "sub x0, x0, #0x10 (16)",
        "tbz x0, #63, #-0x14",
        "add x0, x0, #0x10 (16)",
        "cbz x0, #+0x34",
        "sub x0, x0, #0x8 (8)",
        "tbnz x0, #63, #+0x14",
        "ldp q0, q1, [x2], #32",
        "stp q0, q1, [x1], #32",
        "sub x0, x0, #0x8 (8)",
        "tbz x0, #63, #-0xc",
        "add x0, x0, #0x8 (8)",
        "cbz x0, #+0x14",
        "ldr w3, [x2], #4",
        "str w3, [x1], #4",
        "sub x0, x0, #0x1 (1)",
        "cbnz x0, #-0xc",
        "mov x0, x11",
        "mov x1, x10",
        "mov x2, x7",
        "add x21, x0, x2, lsl #2",
        "add x20, x1, x2, lsl #2",
        "b #+0xe0",
        "cbz x0, #+0xc8",
        "mrs x3, nzcv",
        "sub x0, x1, x2",
        "cmp x0, x7",
        "mov x0, x7",
        "bc.lt #+0x2c",
        "lsl x0, x0, #2",
        "sub x1, x1, x0",
        "sub x2, x2, x0",
        "add x1, x1, #0x4 (4)",
        "add x2, x2, #0x4 (4)",
        "cpyfp [x1]!, [x2]!, x0!",
        "cpyfm [x1]!, [x2]!, x0!",
        "cpyfe [x1]!, [x2]!, x0!",
        "msr nzcv, x3",
        "b #+0x8c",
        "msr nzcv, x3",
        "sub x3, x1, x2",
        "tbz x3, #63, #+0x8",
        "neg x3, x3",
        "sub x3, x3, #0x20 (32)",
        "tbnz x3, #63, #+0x64",
        "sub x1, x1, #0x1c (28)",
        "sub x2, x2, #0x1c (28)",
        "sub x0, x0, #0x8 (8)",
        "tbnz x0, #63, #+0x44",
        "sub x0, x0, #0x8 (8)",
        "tbnz x0, #63, #+0x1c",
        "ldp q0, q1, [x2], #-32",
        "stp q0, q1, [x1], #-32",
        "ldp q0, q1, [x2], #-32",
        "stp q0, q1, [x1], #-32",
        "sub x0, x0, #0x10 (16)",
        "tbz x0, #63, #-0x14",
        "add x0, x0, #0x10 (16)",
        "cbz x0, #+0x3c",
        "sub x0, x0, #0x8 (8)",
        "tbnz x0, #63, #+0x14",
        "ldp q0, q1, [x2], #-32",
        "stp q0, q1, [x1], #-32",
        "sub x0, x0, #0x8 (8)",
        "tbz x0, #63, #-0xc",
        "add x0, x0, #0x8 (8)",
        "cbz x0, #+0x1c",
        "add x1, x1, #0x1c (28)",
        "add x2, x2, #0x1c (28)",
        "ldr w3, [x2], #-4",
        "str w3, [x1], #-4",
        "sub x0, x0, #0x1 (1)",
        "cbnz x0, #-0xc",
        "mov x0, x11",
        "mov x1, x10",
        "mov x2, x7",
        "sub x21, x0, x2, lsl #2",
        "sub x20, x1, x2, lsl #2",
        "mov w7, #0x0",
        "mov x11, x21",
        "mov x10, x20"
      ]
    },
    "rep movsq": {
      "ExpectedInstructionCount": 111,
      "Comment": "0xa5",
      "ExpectedArm64ASM": [
        "ldrsb x22, [x28, #1018]",
        "mov x0, x7",
        "mov x1, x11",
        "mov x2, x10",
        "tbnz w22, #1, #+0xc4",
        "cbz x0, #+0xa8",
        "mrs x3, nzcv",
        "sub x0, x1, x2",
        "cmp x0, x7",
        "mov x0, x7",
        "bc.lt #+0x1c",
        "lsl x0, x0, #3",
        "cpyfp [x1]!, [x2]!, x0!",
        "cpyfm [x1]!, [x2]!, x0!",
        "cpyfe [x1]!, [x2]!, x0!",
        "msr nzcv, x3",
        "b #+0x7c",
        "msr nzcv, x3",
        "sub x3, x1, x2",
        "tbz x3, #63, #+0x8",
        "neg x3, x3",
        "sub x3, x3, #0x20 (32)",
        "tbnz x3, #63, #+0x54",
        "sub x0, x0, #0x4 (4)",
        "tbnz x0, #63, #+0x44",
        "sub x0, x0, #0x4 (4)",
        "tbnz x0, #63, #+0x1c",
        "ldp q0, q1, [x2], #32",
        "stp q0, q1, [x1], #32",
        "ldp q0, q1, [x2], #32",
        "stp q0, q1, [x1], #32",
        "sub x0, x0, #0x8 (8)",
        "tbz x0, #63, #-0x14",
        "add x0, x0, #0x8 (8)",
        "cbz x0, #+0x34",
        "sub x0, x0, #0x4 (4)",
        "tbnz x0, #63, #+0x14",
        "ldp q0, q1, [x2], #32",
        "stp q0, q1, [x1], #32",
        "sub x0, x0, #0x4 (4)",
        "tbz x0, #63, #-0xc",
        "add x0, x0, #0x4 (4)",
        "cbz x0, #+0x14",
        "ldr x3, [x2], #8",
        "str x3, [x1], #8",
        "sub x0, x0, #0x1 (1)",
        "cbnz x0, #-0xc",
        "mov x0, x11",
        "mov x1, x10",
        "mov x2, x7",
        "add x21, x0, x2, lsl #3",
        "add x20, x1, x2, lsl #3",
        "b #+0xe0",
        "cbz x0, #+0xc8",
        "mrs x3, nzcv",
        "sub x0, x1, x2",
        "cmp x0, x7",
        "mov x0, x7",
        "bc.lt #+0x2c",
        "lsl x0, x0, #3",
        "sub x1, x1, x0",
        "sub x2, x2, x0",
        "add x1, x1, #0x8 (8)",
        "add x2, x2, #0x8 (8)",
        "cpyfp [x1]!, [x2]!, x0!",
        "cpyfm [x1]!, [x2]!, x0!",
        "cpyfe [x1]!, [x2]!, x0!",
        "msr nzcv, x3",
        "b #+0x8c",
        "msr nzcv, x3",
        "sub x3, x1, x2",
        "tbz x3, #63, #+0x8",
        "neg x3, x3",
        "sub x3, x3, #0x20 (32)",
        "tbnz x3, #63, #+0x64",
        "sub x1, x1, #0x18 (24)",
        "sub x2, x2, #0x18 (24)",
        "sub x0, x0, #0x4 (4)",
        "tbnz x0, #63, #+0x44",
        "sub x0, x0, #0x4 (4)",
        "tbnz x0, #63, #+0x1c",
        "ldp q0, q1, [x2], #-32",
        "stp q0, q1, [x1], #-32",
        "ldp q0, q1, [x2], #-32",
        "stp q0, q1, [x1], #-32",
        "sub x0, x0, #0x8 (8)",
        "tbz x0, #63, #-0x14",
        "add x0, x0, #0x8 (8)",
        "cbz x0, #+0x3c",
        "sub x0, x0, #0x4 (4)",
        "tbnz x0, #63, #+0x14",
        "ldp q0, q1, [x2], #-32",
        "stp q0, q1, [x1], #-32",
        "sub x0, x0, #0x4 (4)",
        "tbz x0, #63, #-0xc",
        "add x0, x0, #0x4 (4)",
        "cbz x0, #+0x1c",
        "add x1, x1, #0x18 (24)",
        "add x2, x2, #0x18 (24)",
        "ldr x3, [x2], #-8",
        "str x3, [x1], #-8",
        "sub x0, x0, #0x1 (1)",
        "cbnz x0, #-0xc",
        "mov x0, x11",
        "mov x1, x10",
        "mov x2, x7",
        "sub x21, x0, x2, lsl #3",
        "sub x20, x1, x2, lsl #3",
        "mov w7, #0x0",
        "mov x11, x21",
        "mov x10, x20"
      ]
    },
    "cmpsb": {
      "ExpectedInstructionCount": 9,
      "Comment": [
        "0xa6"
      ],
      "ExpectedArm64ASM": [
        "ldrb w20, [x11]",
        "ldrb w21, [x10]",
        "eor x27, x21, x20",
        "lsl w0, w21, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w21, w20",
        "ldrsb x20, [x28, #1018]",
        "add x11, x11, x20",
        "add x10, x10, x20"
      ]
    },
    "cmpsw": {
      "ExpectedInstructionCount": 9,
      "Comment": [
        "0xa7"
      ],
      "ExpectedArm64ASM": [
        "ldrh w20, [x11]",
        "ldrh w21, [x10]",
        "eor x27, x21, x20",
        "lsl w0, w21, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w21, w20",
        "ldrsb x20, [x28, #1018]",
        "add x11, x11, x20, lsl #1",
        "add x10, x10, x20, lsl #1"
      ]
    },
    "cmpsd": {
      "ExpectedInstructionCount": 7,
      "Comment": [
        "0xa7"
      ],
      "ExpectedArm64ASM": [
        "ldr w20, [x11]",
        "ldr w21, [x10]",
        "eor x27, x21, x20",
        "subs w26, w21, w20",
        "ldrsb x20, [x28, #1018]",
        "add x11, x11, x20, lsl #2",
        "add x10, x10, x20, lsl #2"
      ]
    },
    "cmpsq": {
      "ExpectedInstructionCount": 7,
      "Comment": [
        "0xa7"
      ],
      "ExpectedArm64ASM": [
        "ldr x20, [x11]",
        "ldr x21, [x10]",
        "eor x27, x21, x20",
        "subs x26, x21, x20",
        "ldrsb x20, [x28, #1018]",
        "add x11, x11, x20, lsl #3",
        "add x10, x10, x20, lsl #3"
      ]
    },
    "repz cmpsb": {
      "ExpectedInstructionCount": 25,
      "Comment": "0xa6",
      "ExpectedArm64ASM": [
        "cbz x7, #+0x64",
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldrb w26, [x11]",
        "ldrb w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "add x11, x11, #0x1 (1)",
        "add x10, x10, #0x1 (1)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "b #+0x20",
        "ldrb w26, [x11]",
        "ldrb w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "sub x11, x11, #0x1 (1)",
        "sub x10, x10, #0x1 (1)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "eor x20, x27, x26",
        "lsl w0, w27, #24",
        "cmp w0, w26, lsl #24",
        "sub w26, w27, w26",
        "mov x27, x20"
      ]
    },
    "repz cmpsw": {
      "ExpectedInstructionCount": 25,
      "Comment": "0xa7",
      "ExpectedArm64ASM": [
        "cbz x7, #+0x64",
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldrh w26, [x11]",
        "ldrh w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "add x11, x11, #0x2 (2)",
        "add x10, x10, #0x2 (2)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "b #+0x20",
        "ldrh w26, [x11]",
        "ldrh w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "sub x11, x11, #0x2 (2)",
        "sub x10, x10, #0x2 (2)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "eor x20, x27, x26",
        "lsl w0, w27, #16",
        "cmp w0, w26, lsl #16",
        "sub w26, w27, w26",
        "mov x27, x20"
      ]
    },
    "repz cmpsd": {
      "ExpectedInstructionCount": 23,
      "Comment": "0xa7",
      "ExpectedArm64ASM": [
        "cbz x7, #+0x5c",
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldr w26, [x11]",
        "ldr w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "add x11, x11, #0x4 (4)",
        "add x10, x10, #0x4 (4)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "b #+0x20",
        "ldr w26, [x11]",
        "ldr w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "sub x11, x11, #0x4 (4)",
        "sub x10, x10, #0x4 (4)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "eor x20, x27, x26",
        "subs w26, w27, w26",
        "mov x27, x20"
      ]
    },
    "repz cmpsq": {
      "ExpectedInstructionCount": 23,
      "Comment": "0xa7",
      "ExpectedArm64ASM": [
        "cbz x7, #+0x5c",
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldr x26, [x11]",
        "ldr x27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "add x11, x11, #0x8 (8)",
        "add x10, x10, #0x8 (8)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "b #+0x20",
        "ldr x26, [x11]",
        "ldr x27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "sub x11, x11, #0x8 (8)",
        "sub x10, x10, #0x8 (8)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "eor x20, x27, x26",
        "subs x26, x27, x26",
        "mov x27, x20"
      ]
    },
    "repnz cmpsb": {
      "ExpectedInstructionCount": 25,
      "Comment": "0xa6",
      "ExpectedArm64ASM": [
        "cbz x7, #+0x64",
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldrb w26, [x11]",
        "ldrb w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "add x11, x11, #0x1 (1)",
        "add x10, x10, #0x1 (1)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "b #+0x20",
        "ldrb w26, [x11]",
        "ldrb w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "sub x11, x11, #0x1 (1)",
        "sub x10, x10, #0x1 (1)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "eor x20, x27, x26",
        "lsl w0, w27, #24",
        "cmp w0, w26, lsl #24",
        "sub w26, w27, w26",
        "mov x27, x20"
      ]
    },
    "repnz cmpsw": {
      "ExpectedInstructionCount": 25,
      "Comment": "0xa7",
      "ExpectedArm64ASM": [
        "cbz x7, #+0x64",
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldrh w26, [x11]",
        "ldrh w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "add x11, x11, #0x2 (2)",
        "add x10, x10, #0x2 (2)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "b #+0x20",
        "ldrh w26, [x11]",
        "ldrh w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "sub x11, x11, #0x2 (2)",
        "sub x10, x10, #0x2 (2)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "eor x20, x27, x26",
        "lsl w0, w27, #16",
        "cmp w0, w26, lsl #16",
        "sub w26, w27, w26",
        "mov x27, x20"
      ]
    },
    "repnz cmpsd": {
      "ExpectedInstructionCount": 23,
      "Comment": "0xa7",
      "ExpectedArm64ASM": [
        "cbz x7, #+0x5c",
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldr w26, [x11]",
        "ldr w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "add x11, x11, #0x4 (4)",
        "add x10, x10, #0x4 (4)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "b #+0x20",
        "ldr w26, [x11]",
        "ldr w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "sub x11, x11, #0x4 (4)",
        "sub x10, x10, #0x4 (4)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "eor x20, x27, x26",
        "subs w26, w27, w26",
        "mov x27, x20"
      ]
    },
    "repnz cmpsq": {
      "ExpectedInstructionCount": 23,
      "Comment": "0xa7",
      "ExpectedArm64ASM": [
        "cbz x7, #+0x5c",
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldr x26, [x11]",
        "ldr x27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "add x11, x11, #0x8 (8)",
        "add x10, x10, #0x8 (8)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "b #+0x20",
        "ldr x26, [x11]",
        "ldr x27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "sub x11, x11, #0x8 (8)",
        "sub x10, x10, #0x8 (8)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "eor x20, x27, x26",
        "subs x26, x27, x26",
        "mov x27, x20"
      ]
    },
    "stosb": {
      "ExpectedInstructionCount": 3,
      "Comment": "0xaa",
      "ExpectedArm64ASM": [
        "strb w4, [x11]",
        "ldrsb x20, [x28, #1018]",
        "add x11, x11, x20"
      ]
    },
    "stosw": {
      "ExpectedInstructionCount": 3,
      "Comment": "0xab",
      "ExpectedArm64ASM": [
        "strh w4, [x11]",
        "ldrsb x20, [x28, #1018]",
        "add x11, x11, x20, lsl #1"
      ]
    },
    "stosd": {
      "ExpectedInstructionCount": 3,
      "Comment": "0xab",
      "ExpectedArm64ASM": [
        "str w4, [x11]",
        "ldrsb x20, [x28, #1018]",
        "add x11, x11, x20, lsl #2"
      ]
    },
    "stosq": {
      "ExpectedInstructionCount": 3,
      "Comment": "0xab",
      "ExpectedArm64ASM": [
        "str x4, [x11]",
        "ldrsb x20, [x28, #1018]",
        "add x11, x11, x20, lsl #3"
      ]
    },
    "rep stosb": {
      "ExpectedInstructionCount": 23,
      "Comment": "0xaa",
      "ExpectedArm64ASM": [
        "uxtb w20, w4",
        "ldrsb x21, [x28, #1018]",
        "mov x0, x7",
        "mov x1, x11",
        "tbnz w21, #1, #+0x24",
        "cbz x0, #+0x1c",
        "mrs x2, nzcv",
        "setp [x1]!, x0!, x20",
        "setm [x1]!, x0!, x20",
        "sete [x1]!, x0!, x20",
        "msr nzcv, x2",
        "add x11, x11, x7",
        "b #+0x28",
        "cbz x0, #+0x24",
        "sub x1, x1, x0",
        "add x1, x1, #0x1 (1)",
        "mrs x2, nzcv",
        "setp [x1]!, x0!, x20",
        "setm [x1]!, x0!, x20",
        "sete [x1]!, x0!, x20",
        "msr nzcv, x2",
        "sub x11, x11, x7",
        "mov w7, #0x0"
      ]
    },
    "rep stosw": {
      "ExpectedInstructionCount": 55,
      "Comment": "0xab",
      "ExpectedArm64ASM": [
        "uxth w20, w4",
        "ldrsb x21, [x28, #1018]",
        "mov x0, x7",
        "mov x1, x11",
        "tbnz w21, #1, #+0x64",
        "cbz x0, #+0x58",
        "sub x0, x0, #0x10 (16)",
        "tbnz x0, #63, #+0x3c",
        "dup v1.8h, w20",
        "sub x0, x0, #0x10 (16)",
        "tbnz x0, #63, #+0x14",
        "stp q1, q1, [x1], #32",
        "stp q1, q1, [x1], #32",
        "sub x0, x0, #0x20 (32)",
        "tbz x0, #63, #-0xc",
        "add x0, x0, #0x20 (32)",
        "cbz x0, #+0x2c",
        "sub x0, x0, #0x10 (16)",
        "tbnz x0, #63, #+0x10",
        "stp q1, q1, [x1], #32",
        "sub x0, x0, #0x10 (16)",
        "tbz x0, #63, #-0x8",
        "add x0, x0, #0x10 (16)",
        "cbz x0, #+0x10",
        "strh w20, [x1], #2",
        "sub x0, x0, #0x1 (1)",
        "cbnz x0, #-0x8",
        "add x11, x11, x7, lsl #1",
        "b #+0x68",
        "cbz x0, #+0x60",
        "sub x1, x1, #0x1e (30)",
        "sub x0, x0, #0x10 (16)",
        "tbnz x0, #63, #+0x3c",
        "dup v1.8h, w20",
        "sub x0, x0, #0x10 (16)",
        "tbnz x0, #63, #+0x14",
        "stp q1, q1, [x1], #-32",
        "stp q1, q1, [x1], #-32",
        "sub x0, x0, #0x20 (32)",
        "tbz x0, #63, #-0xc",
        "add x0, x0, #0x20 (32)",
        "cbz x0, #+0x30",
        "sub x0, x0, #0x10 (16)",
        "tbnz x0, #63, #+0x10",
        "stp q1, q1, [x1], #-32",
        "sub x0, x0, #0x10 (16)",
        "tbz x0, #63, #-0x8",
        "add x0, x0, #0x10 (16)",
        "cbz x0, #+0x14",
        "add x1, x1, #0x1e (30)",
        "strh w20, [x1], #-2",
        "sub x0, x0, #0x1 (1)",
        "cbnz x0, #-0x8",
        "sub x11, x11, x7, lsl #1",
        "mov w7, #0x0"
      ]
    },
    "rep stosd": {
      "ExpectedInstructionCount": 55,
      "Comment": "0xab",
      "ExpectedArm64ASM": [
        "mov w20, w4",
        "ldrsb x21, [x28, #1018]",
        "mov x0, x7",
        "mov x1, x11",
        "tbnz w21, #1, #+0x64",
        "cbz x0, #+0x58",
        "sub x0, x0, #0x8 (8)",
        "tbnz x0, #63, #+0x3c",
        "dup v1.4s, w20",
        "sub x0, x0, #0x8 (8)",
        "tbnz x0, #63, #+0x14",
        "stp q1, q1, [x1], #32",
        "stp q1, q1, [x1], #32",
        "sub x0, x0, #0x10 (16)",
        "tbz x0, #63, #-0xc",
        "add x0, x0, #0x10 (16)",
        "cbz x0, #+0x2c",
        "sub x0, x0, #0x8 (8)",
        "tbnz x0, #63, #+0x10",
        "stp q1, q1, [x1], #32",
        "sub x0, x0, #0x8 (8)",
        "tbz x0, #63, #-0x8",
        "add x0, x0, #0x8 (8)",
        "cbz x0, #+0x10",
        "str w20, [x1], #4",
        "sub x0, x0, #0x1 (1)",
        "cbnz x0, #-0x8",
        "add x11, x11, x7, lsl #2",
        "b #+0x68",
        "cbz x0, #+0x60",
        "sub x1, x1, #0x1c (28)",
        "sub x0, x0, #0x8 (8)",
        "tbnz x0, #63, #+0x3c",
        "dup v1.4s, w20",
        "sub x0, x0, #0x8 (8)",
        "tbnz x0, #63, #+0x14",
        "stp q1, q1, [x1], #-32",
        "stp q1, q1, [x1], #-32",
        "sub x0, x0, #0x10 (16)",
        "tbz x0, #63, #-0xc",
        "add x0, x0, #0x10 (16)",
        "cbz x0, #+0x30",
        "sub x0, x0, #0x8 (8)",
        "tbnz x0, #63, #+0x10",
        "stp q1, q1, [x1], #-32",
        "sub x0, x0, #0x8 (8)",
        "tbz x0, #63, #-0x8",
        "add x0, x0, #0x8 (8)",
        "cbz x0, #+0x14",
        "add x1, x1, #0x1c (28)",
        "str w20, [x1], #-4",
        "sub x0, x0, #0x1 (1)",
        "cbnz x0, #-0x8",
        "sub x11, x11, x7, lsl #2",
        "mov w7, #0x0"
      ]
    },
    "rep stosq": {
      "ExpectedInstructionCount": 54,
      "Comment": [
        "Unrolling the loop for faster memset can be done.",
        "Taking advantage of ARM MOPs instructions can be done",
        "0xab"
      ],
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #1018]",
        "mov x0, x7",
        "mov x1, x11",
        "tbnz w20, #1, #+0x64",
        "cbz x0, #+0x58",
        "sub x0, x0, #0x4 (4)",
        "tbnz x0, #63, #+0x3c",
        "dup v1.2d, x4",
        "sub x0, x0, #0x4 (4)",
        "tbnz x0, #63, #+0x14",
        "stp q1, q1, [x1], #32",
        "stp q1, q1, [x1], #32",
        "sub x0, x0, #0x8 (8)",
        "tbz x0, #63, #-0xc",
        "add x0, x0, #0x8 (8)",
        "cbz x0, #+0x2c",
        "sub x0, x0, #0x4 (4)",
        "tbnz x0, #63, #+0x10",
        "stp q1, q1, [x1], #32",
        "sub x0, x0, #0x4 (4)",
        "tbz x0, #63, #-0x8",
        "add x0, x0, #0x4 (4)",
        "cbz x0, #+0x10",
        "str x4, [x1], #8",
        "sub x0, x0, #0x1 (1)",
        "cbnz x0, #-0x8",
        "add x11, x11, x7, lsl #3",
        "b #+0x68",
        "cbz x0, #+0x60",
        "sub x1, x1, #0x18 (24)",
        "sub x0, x0, #0x4 (4)",
        "tbnz x0, #63, #+0x3c",
        "dup v1.2d, x4",
        "sub x0, x0, #0x4 (4)",
        "tbnz x0, #63, #+0x14",
        "stp q1, q1, [x1], #-32",
        "stp q1, q1, [x1], #-32",
        "sub x0, x0, #0x8 (8)",
        "tbz x0, #63, #-0xc",
        "add x0, x0, #0x8 (8)",
        "cbz x0, #+0x30",
        "sub x0, x0, #0x4 (4)",
        "tbnz x0, #63, #+0x10",
        "stp q1, q1, [x1], #-32",
        "sub x0, x0, #0x4 (4)",
        "tbz x0, #63, #-0x8",
        "add x0, x0, #0x4 (4)",
        "cbz x0, #+0x14",
        "add x1, x1, #0x18 (24)",
        "str x4, [x1], #-8",
        "sub x0, x0, #0x1 (1)",
        "cbnz x0, #-0x8",
        "sub x11, x11, x7, lsl #3",
        "mov w7, #0x0"
      ]
    },
    "lodsb": {
      "ExpectedInstructionCount": 4,
      "Comment": "0xac",
      "ExpectedArm64ASM": [
        "ldrb w20, [x10]",
        "bfxil x4, x20, #0, #8",
        "ldrsb x20, [x28, #1018]",
        "add x10, x10, x20"
      ]
    },
    "lodsw": {
      "ExpectedInstructionCount": 4,
      "Comment": "0xad",
      "ExpectedArm64ASM": [
        "ldrh w20, [x10]",
        "bfxil x4, x20, #0, #16",
        "ldrsb x20, [x28, #1018]",
        "add x10, x10, x20, lsl #1"
      ]
    },
    "lodsd": {
      "ExpectedInstructionCount": 3,
      "Comment": "0xad",
      "ExpectedArm64ASM": [
        "ldr w4, [x10]",
        "ldrsb x20, [x28, #1018]",
        "add x10, x10, x20, lsl #2"
      ]
    },
    "lodsq": {
      "ExpectedInstructionCount": 3,
      "Comment": "0xad",
      "ExpectedArm64ASM": [
        "ldr x4, [x10]",
        "ldrsb x20, [x28, #1018]",
        "add x10, x10, x20, lsl #3"
      ]
    },
    "rep lodsb": {
      "ExpectedInstructionCount": 17,
      "Comment": "0xac",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x20",
        "cbz x7, #+0x18",
        "ldrb w20, [x10]",
        "bfxil x4, x20, #0, #8",
        "sub x7, x7, #0x1 (1)",
        "add x10, x10, #0x1 (1)",
        "b #-0x14",
        "b #+0x1c",
        "cbz x7, #+0x18",
        "ldrb w20, [x10]",
        "bfxil x4, x20, #0, #8",
        "sub x7, x7, #0x1 (1)",
        "sub x10, x10, #0x1 (1)",
        "b #-0x14"
      ]
    },
    "rep lodsw": {
      "ExpectedInstructionCount": 17,
      "Comment": "0xad",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x20",
        "cbz x7, #+0x18",
        "ldrh w20, [x10]",
        "bfxil x4, x20, #0, #16",
        "sub x7, x7, #0x1 (1)",
        "add x10, x10, #0x2 (2)",
        "b #-0x14",
        "b #+0x1c",
        "cbz x7, #+0x18",
        "ldrh w20, [x10]",
        "bfxil x4, x20, #0, #16",
        "sub x7, x7, #0x1 (1)",
        "sub x10, x10, #0x2 (2)",
        "b #-0x14"
      ]
    },
    "rep lodsd": {
      "ExpectedInstructionCount": 15,
      "Comment": "0xad",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x1c",
        "cbz x7, #+0x14",
        "ldr w4, [x10]",
        "sub x7, x7, #0x1 (1)",
        "add x10, x10, #0x4 (4)",
        "b #-0x10",
        "b #+0x18",
        "cbz x7, #+0x14",
        "ldr w4, [x10]",
        "sub x7, x7, #0x1 (1)",
        "sub x10, x10, #0x4 (4)",
        "b #-0x10"
      ]
    },
    "rep lodsq": {
      "ExpectedInstructionCount": 15,
      "Comment": "0xad",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x1c",
        "cbz x7, #+0x14",
        "ldr x4, [x10]",
        "sub x7, x7, #0x1 (1)",
        "add x10, x10, #0x8 (8)",
        "b #-0x10",
        "b #+0x18",
        "cbz x7, #+0x14",
        "ldr x4, [x10]",
        "sub x7, x7, #0x1 (1)",
        "sub x10, x10, #0x8 (8)",
        "b #-0x10"
      ]
    },
    "scasb": {
      "ExpectedInstructionCount": 7,
      "Comment": "0xae",
      "ExpectedArm64ASM": [
        "ldrb w20, [x11]",
        "eor x27, x4, x20",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, w20",
        "ldrsb x20, [x28, #1018]",
        "add x11, x11, x20"
      ]
    },
    "scasw": {
      "ExpectedInstructionCount": 7,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldrh w20, [x11]",
        "eor x27, x4, x20",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, w20",
        "ldrsb x20, [x28, #1018]",
        "add x11, x11, x20, lsl #1"
      ]
    },
    "scasd": {
      "ExpectedInstructionCount": 5,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldr w20, [x11]",
        "eor x27, x4, x20",
        "subs w26, w4, w20",
        "ldrsb x20, [x28, #1018]",
        "add x11, x11, x20, lsl #2"
      ]
    },
    "scasq": {
      "ExpectedInstructionCount": 5,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldr x20, [x11]",
        "eor x27, x4, x20",
        "subs x26, x4, x20",
        "ldrsb x20, [x28, #1018]",
        "add x11, x11, x20, lsl #3"
      ]
    },
    "repz scasb": {
      "ExpectedInstructionCount": 23,
      "Comment": "0xae",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x2c",
        "cbz x7, #+0x24",
        "ldrb w20, [x11]",
        "eor x27, x4, x20",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "add x11, x11, #0x1 (1)",
        "b.eq #-0x20",
        "b #+0x28",
        "cbz x7, #+0x24",
        "ldrb w20, [x11]",
        "eor x27, x4, x20",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "sub x11, x11, #0x1 (1)",
        "b.eq #-0x20"
      ]
    },
    "repz scasw": {
      "ExpectedInstructionCount": 23,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x2c",
        "cbz x7, #+0x24",
        "ldrh w20, [x11]",
        "eor x27, x4, x20",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "add x11, x11, #0x2 (2)",
        "b.eq #-0x20",
        "b #+0x28",
        "cbz x7, #+0x24",
        "ldrh w20, [x11]",
        "eor x27, x4, x20",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "sub x11, x11, #0x2 (2)",
        "b.eq #-0x20"
      ]
    },
    "repz scasd": {
      "ExpectedInstructionCount": 19,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "cbz x7, #+0x1c",
        "ldr w20, [x11]",
        "eor x27, x4, x20",
        "subs w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "add x11, x11, #0x4 (4)",
        "b.eq #-0x18",
        "b #+0x20",
        "cbz x7, #+0x1c",
        "ldr w20, [x11]",
        "eor x27, x4, x20",
        "subs w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "sub x11, x11, #0x4 (4)",
        "b.eq #-0x18"
      ]
    },
    "repz scasq": {
      "ExpectedInstructionCount": 19,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "cbz x7, #+0x1c",
        "ldr x20, [x11]",
        "eor x27, x4, x20",
        "subs x26, x4, x20",
        "sub x7, x7, #0x1 (1)",
        "add x11, x11, #0x8 (8)",
        "b.eq #-0x18",
        "b #+0x20",
        "cbz x7, #+0x1c",
        "ldr x20, [x11]",
        "eor x27, x4, x20",
        "subs x26, x4, x20",
        "sub x7, x7, #0x1 (1)",
        "sub x11, x11, #0x8 (8)",
        "b.eq #-0x18"
      ]
    },
    "repnz scasb": {
      "ExpectedInstructionCount": 23,
      "Comment": "0xae",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x2c",
        "cbz x7, #+0x24",
        "ldrb w20, [x11]",
        "eor x27, x4, x20",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "add x11, x11, #0x1 (1)",
        "b.ne #-0x20",
        "b #+0x28",
        "cbz x7, #+0x24",
        "ldrb w20, [x11]",
        "eor x27, x4, x20",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "sub x11, x11, #0x1 (1)",
        "b.ne #-0x20"
      ]
    },
    "repnz scasw": {
      "ExpectedInstructionCount": 23,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x2c",
        "cbz x7, #+0x24",
        "ldrh w20, [x11]",
        "eor x27, x4, x20",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "add x11, x11, #0x2 (2)",
        "b.ne #-0x20",
        "b #+0x28",
        "cbz x7, #+0x24",
        "ldrh w20, [x11]",
        "eor x27, x4, x20",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "sub x11, x11, #0x2 (2)",
        "b.ne #-0x20"
      ]
    },
    "repnz scasd": {
      "ExpectedInstructionCount": 19,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "cbz x7, #+0x1c",
        "ldr w20, [x11]",
        "eor x27, x4, x20",
        "subs w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "add x11, x11, #0x4 (4)",
        "b.ne #-0x18",
        "b #+0x20",
        "cbz x7, #+0x1c",
        "ldr w20, [x11]",
        "eor x27, x4, x20",
        "subs w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "sub x11, x11, #0x4 (4)",
        "b.ne #-0x18"
      ]
    },
    "repnz scasq": {
      "ExpectedInstructionCount": 19,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "cbz x7, #+0x1c",
        "ldr x20, [x11]",
        "eor x27, x4, x20",
        "subs x26, x4, x20",
        "sub x7, x7, #0x1 (1)",
        "add x11, x11, #0x8 (8)",
        "b.ne #-0x18",
        "b #+0x20",
        "cbz x7, #+0x1c",
        "ldr x20, [x11]",
        "eor x27, x4, x20",
        "subs x26, x4, x20",
        "sub x7, x7, #0x1 (1)",
        "sub x11, x11, #0x8 (8)",
        "b.ne #-0x18"
      ]
    }
  }
}