{
  "Features": {
    "Bitness": 64,
    "EnabledHostFeatures": [],
    "DisabledHostFeatures": [
      "SVE128",
      "SVE256",
      "RPRES",
      "AFP"
    ]
  },
  "Comment": [
    "Instructions that explicitly push against the limits of ARM's loadstore instructions"
  ],
  "Instructions": {
    "movzx rax, byte [ecx - 257]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "sub x20, x5, #0x101 (257)",
        "mov w20, w20",
        "ldrb w4, [x20]"
      ]
    },
    "movzx rax, byte [ecx - 256]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "sub x20, x5, #0x100 (256)",
        "mov w20, w20",
        "ldrb w4, [x20]"
      ]
    },
    "movzx rax, byte [ecx + 255]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "add x20, x5, #0xff (255)",
        "mov w20, w20",
        "ldrb w4, [x20]"
      ]
    },
    "movzx rax, byte [ecx + 256]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "add x20, x5, #0x100 (256)",
        "mov w20, w20",
        "ldrb w4, [x20]"
      ]
    },
    "movzx rax, byte [ecx + 4095]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "add x20, x5, #0xfff (4095)",
        "mov w20, w20",
        "ldrb w4, [x20]"
      ]
    },
    "movzx rax, byte [ecx + 4096]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "add x20, x5, #0x1000 (4096)",
        "mov w20, w20",
        "ldrb w4, [x20]"
      ]
    },
    "movzx rax, word [ecx - 257]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "sub x20, x5, #0x101 (257)",
        "mov w20, w20",
        "ldrh w4, [x20]"
      ]
    },
    "movzx rax, word [ecx - 256]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "sub x20, x5, #0x100 (256)",
        "mov w20, w20",
        "ldrh w4, [x20]"
      ]
    },
    "movzx rax, word [ecx + 255]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "add x20, x5, #0xff (255)",
        "mov w20, w20",
        "ldrh w4, [x20]"
      ]
    },
    "movzx rax, word [ecx + 256]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "add x20, x5, #0x100 (256)",
        "mov w20, w20",
        "ldrh w4, [x20]"
      ]
    },
    "movzx rax, word [ecx + 8190]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0x1ffe",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldrh w4, [x20]"
      ]
    },
    "movzx rax, word [ecx + 8191]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0x1fff",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldrh w4, [x20]"
      ]
    },
    "movzx rax, word [ecx + 8192]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "add x20, x5, #0x2000 (8192)",
        "mov w20, w20",
        "ldrh w4, [x20]"
      ]
    },
    "mov eax, dword [ecx - 257]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "sub x20, x5, #0x101 (257)",
        "mov w20, w20",
        "ldr w4, [x20]"
      ]
    },
    "mov eax, dword [ecx - 256]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "sub x20, x5, #0x100 (256)",
        "mov w20, w20",
        "ldr w4, [x20]"
      ]
    },
    "mov eax, dword [ecx + 255]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "add x20, x5, #0xff (255)",
        "mov w20, w20",
        "ldr w4, [x20]"
      ]
    },
    "mov eax, dword [ecx + 256]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "add x20, x5, #0x100 (256)",
        "mov w20, w20",
        "ldr w4, [x20]"
      ]
    },
    "mov eax, dword [ecx + 16380]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0x3ffc",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldr w4, [x20]"
      ]
    },
    "mov eax, dword [ecx + 16381]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0x3ffd",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldr w4, [x20]"
      ]
    },
    "mov eax, dword [ecx + 16382]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0x3ffe",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldr w4, [x20]"
      ]
    },
    "mov eax, dword [ecx + 16383]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0x3fff",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldr w4, [x20]"
      ]
    },
    "mov eax, dword [ecx + 16384]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "add x20, x5, #0x4000 (16384)",
        "mov w20, w20",
        "ldr w4, [x20]"
      ]
    },
    "mov rax, qword [ecx - 257]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "sub x20, x5, #0x101 (257)",
        "mov w20, w20",
        "ldr x4, [x20]"
      ]
    },
    "mov rax, qword [ecx - 256]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "sub x20, x5, #0x100 (256)",
        "mov w20, w20",
        "ldr x4, [x20]"
      ]
    },
    "mov rax, qword [ecx + 255]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "add x20, x5, #0xff (255)",
        "mov w20, w20",
        "ldr x4, [x20]"
      ]
    },
    "mov rax, qword [ecx + 256]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "add x20, x5, #0x100 (256)",
        "mov w20, w20",
        "ldr x4, [x20]"
      ]
    },
    "mov rax, qword [ecx + 32760]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0x7ff8",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldr x4, [x20]"
      ]
    },
    "mov rax, qword [ecx + 32761]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0x7ff9",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldr x4, [x20]"
      ]
    },
    "mov rax, qword [ecx + 32762]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0x7ffa",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldr x4, [x20]"
      ]
    },
    "mov rax, qword [ecx + 32763]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0x7ffb",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldr x4, [x20]"
      ]
    },
    "mov rax, qword [ecx + 32764]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0x7ffc",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldr x4, [x20]"
      ]
    },
    "mov rax, qword [ecx + 32765]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0x7ffd",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldr x4, [x20]"
      ]
    },
    "mov rax, qword [ecx + 32766]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0x7ffe",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldr x4, [x20]"
      ]
    },
    "mov rax, qword [ecx + 32767]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0x7fff",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldr x4, [x20]"
      ]
    },
    "mov rax, qword [ecx + 32768]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "add x20, x5, #0x8000 (32768)",
        "mov w20, w20",
        "ldr x4, [x20]"
      ]
    },
    "movzx rax, byte [rcx - 257]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov x20, #0xfffffffffffffeff",
        "ldrb w4, [x5, x20, sxtx]"
      ]
    },
    "movzx rax, byte [rcx - 256]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldurb w4, [x5, #-256]"
      ]
    },
    "movzx rax, byte [rcx + 255]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldrb w4, [x5, #255]"
      ]
    },
    "movzx rax, byte [rcx + 256]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldrb w4, [x5, #256]"
      ]
    },
    "movzx rax, byte [rcx + 4095]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldrb w4, [x5, #4095]"
      ]
    },
    "movzx rax, byte [rcx + 4096]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov w20, #0x1000",
        "ldrb w4, [x5, x20, sxtx]"
      ]
    },
    "movzx rax, word [rcx - 257]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov x20, #0xfffffffffffffeff",
        "ldrh w4, [x5, x20, sxtx]"
      ]
    },
    "movzx rax, word [rcx - 256]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldurh w4, [x5, #-256]"
      ]
    },
    "movzx rax, word [rcx + 255]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldurh w4, [x5, #255]"
      ]
    },
    "movzx rax, word [rcx + 256]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldrh w4, [x5, #256]"
      ]
    },
    "movzx rax, word [rcx + 8190]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldrh w4, [x5, #8190]"
      ]
    },
    "movzx rax, word [rcx + 8191]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov w20, #0x1fff",
        "ldrh w4, [x5, x20, sxtx]"
      ]
    },
    "movzx rax, word [rcx + 8192]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov w20, #0x2000",
        "ldrh w4, [x5, x20, sxtx]"
      ]
    },
    "mov eax, dword [rcx - 257]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov x20, #0xfffffffffffffeff",
        "ldr w4, [x5, x20, sxtx]"
      ]
    },
    "mov eax, dword [rcx - 256]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldur w4, [x5, #-256]"
      ]
    },
    "mov eax, dword [rcx + 255]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldur w4, [x5, #255]"
      ]
    },
    "mov eax, dword [rcx + 256]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldr w4, [x5, #256]"
      ]
    },
    "mov eax, dword [rcx + 16380]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldr w4, [x5, #16380]"
      ]
    },
    "mov eax, dword [rcx + 16381]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov w20, #0x3ffd",
        "ldr w4, [x5, x20, sxtx]"
      ]
    },
    "mov eax, dword [rcx + 16382]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov w20, #0x3ffe",
        "ldr w4, [x5, x20, sxtx]"
      ]
    },
    "mov eax, dword [rcx + 16383]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov w20, #0x3fff",
        "ldr w4, [x5, x20, sxtx]"
      ]
    },
    "mov eax, dword [rcx + 16384]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov w20, #0x4000",
        "ldr w4, [x5, x20, sxtx]"
      ]
    },
    "mov rax, qword [rcx - 257]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov x20, #0xfffffffffffffeff",
        "ldr x4, [x5, x20, sxtx]"
      ]
    },
    "mov rax, qword [rcx - 256]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldur x4, [x5, #-256]"
      ]
    },
    "mov rax, qword [rcx + 255]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldur x4, [x5, #255]"
      ]
    },
    "mov rax, qword [rcx + 256]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldr x4, [x5, #256]"
      ]
    },
    "mov rax, qword [rcx + 32760]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldr x4, [x5, #32760]"
      ]
    },
    "mov rax, qword [rcx + 32761]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov w20, #0x7ff9",
        "ldr x4, [x5, x20, sxtx]"
      ]
    },
    "mov rax, qword [rcx + 32762]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov w20, #0x7ffa",
        "ldr x4, [x5, x20, sxtx]"
      ]
    },
    "mov rax, qword [rcx + 32763]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov w20, #0x7ffb",
        "ldr x4, [x5, x20, sxtx]"
      ]
    },
    "mov rax, qword [rcx + 32764]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov w20, #0x7ffc",
        "ldr x4, [x5, x20, sxtx]"
      ]
    },
    "mov rax, qword [rcx + 32765]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov w20, #0x7ffd",
        "ldr x4, [x5, x20, sxtx]"
      ]
    },
    "mov rax, qword [rcx + 32766]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov w20, #0x7ffe",
        "ldr x4, [x5, x20, sxtx]"
      ]
    },
    "mov rax, qword [rcx + 32767]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov w20, #0x7fff",
        "ldr x4, [x5, x20, sxtx]"
      ]
    },
    "mov rax, qword [rcx + 32768]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov w20, #0x8000",
        "ldr x4, [x5, x20, sxtx]"
      ]
    },
    "movss xmm0, [rcx + 16379]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov w20, #0x3ffb",
        "ldr s16, [x5, x20, sxtx]"
      ]
    },
    "movss xmm0, [rcx + 16380]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldr s16, [x5, #16380]"
      ]
    },
    "movss xmm0, [rcx + 16381]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov w20, #0x3ffd",
        "ldr s16, [x5, x20, sxtx]"
      ]
    },
    "movss xmm0, [rcx - 257]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov x20, #0xfffffffffffffeff",
        "ldr s16, [x5, x20, sxtx]"
      ]
    },
    "movss xmm0, [rcx - 256]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldur s16, [x5, #-256]"
      ]
    },
    "movss xmm0, [rcx + 255]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldur s16, [x5, #255]"
      ]
    },
    "movss xmm0, [rcx + 256]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldr s16, [x5, #256]"
      ]
    },
    "movsd xmm0, [rcx + 32759]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov w20, #0x7ff7",
        "ldr d16, [x5, x20, sxtx]"
      ]
    },
    "movsd xmm0, [rcx + 32760]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldr d16, [x5, #32760]"
      ]
    },
    "movsd xmm0, [rcx + 32761]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov w20, #0x7ff9",
        "ldr d16, [x5, x20, sxtx]"
      ]
    },
    "movsd xmm0, [rcx - 257]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov x20, #0xfffffffffffffeff",
        "ldr d16, [x5, x20, sxtx]"
      ]
    },
    "movsd xmm0, [rcx - 256]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldur d16, [x5, #-256]"
      ]
    },
    "movsd xmm0, [rcx + 255]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldur d16, [x5, #255]"
      ]
    },
    "movsd xmm0, [rcx + 256]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldr d16, [x5, #256]"
      ]
    },
    "movq xmm0, [rcx + 65519]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov w20, #0xffef",
        "ldr d16, [x5, x20, sxtx]"
      ]
    },
    "movq xmm0, [rcx + 65520]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov w20, #0xfff0",
        "ldr d16, [x5, x20, sxtx]"
      ]
    },
    "movq xmm0, [rcx + 65521]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov w20, #0xfff1",
        "ldr d16, [x5, x20, sxtx]"
      ]
    },
    "movq xmm0, [rcx - 257]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "mov x20, #0xfffffffffffffeff",
        "ldr d16, [x5, x20, sxtx]"
      ]
    },
    "movq xmm0, [rcx - 256]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldur d16, [x5, #-256]"
      ]
    },
    "movq xmm0, [rcx + 255]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldur d16, [x5, #255]"
      ]
    },
    "movq xmm0, [rcx + 256]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldr d16, [x5, #256]"
      ]
    },
    "movss xmm0, [ecx + 16379]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0x3ffb",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldr s16, [x20]"
      ]
    },
    "movss xmm0, [ecx + 16380]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0x3ffc",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldr s16, [x20]"
      ]
    },
    "movss xmm0, [ecx + 16381]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0x3ffd",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldr s16, [x20]"
      ]
    },
    "movss xmm0, [ecx - 257]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "sub x20, x5, #0x101 (257)",
        "mov w20, w20",
        "ldr s16, [x20]"
      ]
    },
    "movss xmm0, [ecx - 256]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "sub x20, x5, #0x100 (256)",
        "mov w20, w20",
        "ldr s16, [x20]"
      ]
    },
    "movss xmm0, [ecx + 255]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "add x20, x5, #0xff (255)",
        "mov w20, w20",
        "ldr s16, [x20]"
      ]
    },
    "movss xmm0, [ecx + 256]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "add x20, x5, #0x100 (256)",
        "mov w20, w20",
        "ldr s16, [x20]"
      ]
    },
    "movsd xmm0, [ecx + 32759]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0x7ff7",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldr d16, [x20]"
      ]
    },
    "movsd xmm0, [ecx + 32760]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0x7ff8",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldr d16, [x20]"
      ]
    },
    "movsd xmm0, [ecx + 32761]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0x7ff9",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldr d16, [x20]"
      ]
    },
    "movsd xmm0, [ecx - 257]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "sub x20, x5, #0x101 (257)",
        "mov w20, w20",
        "ldr d16, [x20]"
      ]
    },
    "movsd xmm0, [ecx - 256]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "sub x20, x5, #0x100 (256)",
        "mov w20, w20",
        "ldr d16, [x20]"
      ]
    },
    "movsd xmm0, [ecx + 255]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "add x20, x5, #0xff (255)",
        "mov w20, w20",
        "ldr d16, [x20]"
      ]
    },
    "movsd xmm0, [ecx + 256]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "add x20, x5, #0x100 (256)",
        "mov w20, w20",
        "ldr d16, [x20]"
      ]
    },
    "movq xmm0, [ecx + 65519]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0xffef",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldr d16, [x20]"
      ]
    },
    "movq xmm0, [ecx + 65520]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0xfff0",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldr d16, [x20]"
      ]
    },
    "movq xmm0, [ecx + 65521]": {
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "mov w20, #0xfff1",
        "add x20, x5, x20",
        "mov w20, w20",
        "ldr d16, [x20]"
      ]
    },
    "movq xmm0, [ecx - 257]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "sub x20, x5, #0x101 (257)",
        "mov w20, w20",
        "ldr d16, [x20]"
      ]
    },
    "movq xmm0, [ecx - 256]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "sub x20, x5, #0x100 (256)",
        "mov w20, w20",
        "ldr d16, [x20]"
      ]
    },
    "movq xmm0, [ecx + 255]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "add x20, x5, #0xff (255)",
        "mov w20, w20",
        "ldr d16, [x20]"
      ]
    },
    "movq xmm0, [ecx + 256]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "add x20, x5, #0x100 (256)",
        "mov w20, w20",
        "ldr d16, [x20]"
      ]
    },
    "prefetch [rcx - 257]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "sub x20, x5, #0x101 (257)",
        "prfm pldl1keep, [x20]"
      ]
    },
    "prefetch [rcx - 256]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "sub x20, x5, #0x100 (256)",
        "prfm pldl1keep, [x20]"
      ]
    },
    "prefetch [rcx + 255]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "add x20, x5, #0xff (255)",
        "prfm pldl1keep, [x20]"
      ]
    },
    "prefetch [rcx + 256]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "add x20, x5, #0x100 (256)",
        "prfm pldl1keep, [x20]"
      ]
    },
    "prefetch [rcx + 32760]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "mov w20, #0x7ff8",
        "add x20, x5, x20",
        "prfm pldl1keep, [x20]"
      ]
    },
    "prefetch [rcx + 32761]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "mov w20, #0x7ff9",
        "add x20, x5, x20",
        "prfm pldl1keep, [x20]"
      ]
    },
    "prefetch [rax + rcx*1]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "add x20, x4, x5",
        "prfm pldl1keep, [x20]"
      ]
    },
    "prefetch [rax + rcx*2]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "add x20, x4, x5, lsl #1",
        "prfm pldl1keep, [x20]"
      ]
    },
    "prefetch [rax + rcx*4]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "add x20, x4, x5, lsl #2",
        "prfm pldl1keep, [x20]"
      ]
    },
    "prefetch [rax + rcx*8]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "add x20, x4, x5, lsl #3",
        "prfm pldl1keep, [x20]"
      ]
    },
    "movzx ebx, byte [rax + rcx*1]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldrb w7, [x4, x5, sxtx]"
      ]
    },
    "movzx ebx, byte [rax + rcx*2]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "add x20, x4, x5, lsl #1",
        "ldrb w7, [x20]"
      ]
    },
    "movzx ebx, byte [rax + rcx*4]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "add x20, x4, x5, lsl #2",
        "ldrb w7, [x20]"
      ]
    },
    "movzx ebx, byte [rax + rcx*8]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "add x20, x4, x5, lsl #3",
        "ldrb w7, [x20]"
      ]
    },
    "movzx ebx, word [rax + rcx*1]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldrh w7, [x4, x5, sxtx]"
      ]
    },
    "movzx ebx, word [rax + rcx*2]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldrh w7, [x4, x5, sxtx #1]"
      ]
    },
    "movzx ebx, word [rax + rcx*4]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "add x20, x4, x5, lsl #2",
        "ldrh w7, [x20]"
      ]
    },
    "movzx ebx, word [rax + rcx*8]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "add x20, x4, x5, lsl #3",
        "ldrh w7, [x20]"
      ]
    },
    "mov ebx, [rax + rcx*1]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldr w7, [x4, x5, sxtx]"
      ]
    },
    "mov ebx, [rax + rcx*2]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "add x20, x4, x5, lsl #1",
        "ldr w7, [x20]"
      ]
    },
    "mov ebx, [rax + rcx*4]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldr w7, [x4, x5, sxtx #2]"
      ]
    },
    "mov ebx, [rax + rcx*8]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "add x20, x4, x5, lsl #3",
        "ldr w7, [x20]"
      ]
    },
    "mov rbx, [rax + rcx*1]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldr x7, [x4, x5, sxtx]"
      ]
    },
    "mov rbx, [rax + rcx*2]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "add x20, x4, x5, lsl #1",
        "ldr x7, [x20]"
      ]
    },
    "mov rbx, [rax + rcx*4]": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "add x20, x4, x5, lsl #2",
        "ldr x7, [x20]"
      ]
    },
    "mov rbx, [rax + rcx*8]": {
      "ExpectedInstructionCount": 1,
      "ExpectedArm64ASM": [
        "ldr x7, [x4, x5, sxtx #3]"
      ]
    },
    "mov ebx, fs:0x14": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "ldr x20, [x28, #968]",
        "ldr w7, [x20, #20]"
      ]
    },
    "mov rbx, gs:0x14": {
      "ExpectedInstructionCount": 2,
      "ExpectedArm64ASM": [
        "ldr x20, [x28, #960]",
        "ldur x7, [x20, #20]"
      ]
    },
    "Multiple segment registers": {
      "x86Insts": [
        "mov rax, gs:0x100",
        "mov rbx, gs:0x14"
      ],
      "ExpectedInstructionCount": 4,
      "ExpectedArm64ASM": [
        "ldr x20, [x28, #960]",
        "ldr x4, [x20, #256]",
        "ldr x20, [x28, #960]",
        "ldur x7, [x20, #20]"
      ]
    },
    "vmovdqu ymm7,yword [rsi+0x60]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "ldr q23, [x10, #96]",
        "ldr q2, [x10, #112]",
        "str q2, [x28, #128]"
      ]
    },
    "vmovdqu ymm7,yword [rsi+0x120]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "ldr q23, [x10, #288]",
        "ldr q2, [x10, #304]",
        "str q2, [x28, #128]"
      ]
    },
    "vmovdqu ymm7,yword [rsi-0x60]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "ldur q23, [x10, #-96]",
        "ldur q2, [x10, #-80]",
        "str q2, [x28, #128]"
      ]
    },
    "vmovdqu ymm7,yword [rsi-0x400]": {
      "ExpectedInstructionCount": 5,
      "ExpectedArm64ASM": [
        "mov x20, #0xfffffffffffffc00",
        "ldr q23, [x10, x20, sxtx]",
        "mov x20, #0xfffffffffffffc10",
        "ldr q2, [x10, x20, sxtx]",
        "str q2, [x28, #128]"
      ]
    },
    "vmovdqu ymm7,yword [rsi-0x420]": {
      "ExpectedInstructionCount": 5,
      "ExpectedArm64ASM": [
        "mov x20, #0xfffffffffffffbe0",
        "ldr q23, [x10, x20, sxtx]",
        "mov x20, #0xfffffffffffffbf0",
        "ldr q2, [x10, x20, sxtx]",
        "str q2, [x28, #128]"
      ]
    },
    "vmovdqu ymm7,yword [rsi+0x3d0]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "ldr q23, [x10, #976]",
        "ldr q2, [x10, #992]",
        "str q2, [x28, #128]"
      ]
    },
    "vmovdqu ymm7,yword [rsi+0x400]": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "ldr q23, [x10, #1024]",
        "ldr q2, [x10, #1040]",
        "str q2, [x28, #128]"
      ]
    },
    "vmovdqa yword [rcx+0x60],ymm1": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "ldr q2, [x28, #32]",
        "str q17, [x5, #96]",
        "str q2, [x5, #112]"
      ]
    },
    "vmovdqa yword [rcx+0x3d0],ymm1": {
      "ExpectedInstructionCount": 3,
      "ExpectedArm64ASM": [
        "ldr q2, [x28, #32]",
        "str q17, [x5, #976]",
        "str q2, [x5, #992]"
      ]
    },
    "vmovdqa yword [rcx-0x3d0],ymm1": {
      "ExpectedInstructionCount": 5,
      "ExpectedArm64ASM": [
        "ldr q2, [x28, #32]",
        "mov x20, #0xfffffffffffffc30",
        "str q17, [x5, x20, sxtx]",
        "mov x20, #0xfffffffffffffc40",
        "str q2, [x5, x20, sxtx]"
      ]
    },
    "vmovdqa yword [rcx+rsi-0x3d0],ymm1": {
      "ExpectedInstructionCount": 7,
      "ExpectedArm64ASM": [
        "ldr q2, [x28, #32]",
        "add x20, x5, x10",
        "mov x21, #0xfffffffffffffc30",
        "str q17, [x20, x21, sxtx]",
        "add x20, x5, x10",
        "mov x21, #0xfffffffffffffc40",
        "str q2, [x20, x21, sxtx]"
      ]
    }
  }
}