steam-frame/FEX-Emu--FEX
1
0 Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2026-10-14 09:00:40 +02:00
Code Issues Packages Projects Releases 67 Wiki Activity
11,772 Commits 11 Branches 71 Tags
ff2c2f1e1f8ddc8da2a4f6151646725a3f0f9504
Commit Graph
1918 Commits
Author SHA1 Message Date
Lioncache ff2c2f1e1f Addressing: Remove unnecessary assert in LoadEffectiveAddress() 
ilog2 already has an assert for this.
 2025-03-28 06:08:08 -04:00
Lioncache 54dbb9f248 OpcodeDispatcher: Fix potential for uninitialized value use in RCRSmallerOp() 
If Src isn't a constant, then no value is actually assigned to SrcConst, so this
can result in uninitialized arithmetic being performed
 2025-03-28 04:45:40 -04:00
Ryan Houdek 21233430aa Merge pull request #4446 from lioncash/cond 
OpcodeDispatcher: Remove unnecessary 128-bit check in VPGATHER()
 2025-03-27 20:30:49 -07:00
Ryan Houdek bd1d6820b7 Merge pull request #4438 from Sonicadvance1/static_analysis_wars 
Static analysis warning fixes
 2025-03-27 20:30:37 -07:00
Lioncache 40b1c32008 OpcodeDispatcher: Remove unnecessary 128-bit check in VPGATHER() 
This is already guaranteed to be true, since it's checked in the outer if,
so this can just be a regular else statement.
 2025-03-27 23:08:59 -04:00
Ryan Houdek b5ed804578 Merge pull request #4444 from lioncash/jitcond 
JIT: Simplify SVE 256 operation asserts
 2025-03-27 19:46:23 -07:00
Ryan Houdek ec976f3f75 Merge pull request #4435 from alyssarosenzweig/opt/pall-pf-af 
Pair PF/AF when spilling static regs
 2025-03-27 19:45:29 -07:00
Lioncache 35ee12e7e9 Addressing: Amend binary AND into logical AND in SelectAddressMode() 
Bitwise AND here is a little odd and was likely intended to be a logical AND.
 2025-03-27 17:29:08 -04:00
Lioncache 4497ab8844 JIT: Simplify SVE 256 operation asserts 
We can make these slightly less verbose.
 2025-03-27 16:55:20 -04:00
Alyssa Rosenzweig cb91d585c3 Arm64Emitter: pair pf/af load/store 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-27 11:07:00 -04:00
Alyssa Rosenzweig 42ea711850 CoreState: squish and rearrange pf_raw/af_raw 
to allow next commit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-27 11:04:08 -04:00
Alyssa Rosenzweig 2cfc42bd6a Arm64Emitter: simplify and fix !preserve_all regs 
stop doing weird special cases. just dump all the regs except what aapcs64 says
we don't have to.

this fixes saving x18 across thunks and things. so probably fixes things *cry*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-27 10:07:27 -04:00
Ryan Houdek 003de2b659 JIT: static analysis warnings 2025-03-27 04:36:41 -07:00
Ryan Houdek 8f9d818368 OpcodeDispathcer: static analysis warnings 2025-03-27 04:26:40 -07:00
Alyssa Rosenzweig 7c42c7798c Arm64Emitter: fix a bunch of preserve_all 
* x18 wasn't getting spilled even though it was supposed to be.
* arm64ec preserve_all definitions were all messed up, specialize these to fix.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-26 16:47:39 -04:00
Ryan Houdek ab9123a427 JIT: Fix typo in VSha256U1 2025-03-25 18:19:37 -07:00
Alyssa Rosenzweig f87edbe1cb JIT: eliminate a zext in bfi 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-25 17:36:59 -04:00
Tony Wasserka 7efd827e78 Merge pull request #4378 from bylaws/volmd 
Implement PE volatile metadata support
 2025-03-25 10:23:53 +01:00
Ryan Houdek d48413cbec Merge pull request #4426 from alyssarosenzweig/opt/shld-improvements 
Drop some masking in shld
 2025-03-24 19:24:51 -07:00
Billy Laws 7a5e08c5ab FEXCore: Use TSO range information when emitting IR 2025-03-24 22:01:49 +00:00
Billy Laws 642903a7bf FEXCore: Support tracking TSO range information 2025-03-24 22:01:49 +00:00
Alyssa Rosenzweig b86cbda03d OpcodeDispatcher: drop useless mask in trivial cmpxchg 
hit by upcoming opt pass, but we don't want to depend on that pass for that.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-24 16:17:04 -04:00
Alyssa Rosenzweig e26b9b12fa OpcodeDispatcher: drop useless zext in shld 
this gets deleted by an upcoming opt pass, but we shouldn't be depending on
the opt pass for it!

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-24 16:00:24 -04:00
Ryan Houdek 9a92f6f743 FEXCore: Remove CPUID option for SHA 
Instead use the HostFeatures option that exists which is controlled by
the {enable,disable}crypto option.
 2025-03-21 19:43:38 -07:00
Ryan Houdek ab7f6484cf Merge pull request #4414 from pmatos/AddrMode-DeusEx 
Fix address modes calculation on 32bit guests
 2025-03-20 13:21:53 -07:00
Paulo Matos b18f148575 Abstract AddressMode into its own header 
Also refactor usage of utility functions into x87 Stack Optimization Pass.
 2025-03-20 11:41:26 +01:00
Alyssa Rosenzweig 61d2a09827 OpcodeDispatcher: fix BT flags 
ZF needs to be preserved.

the new code is the same instr count on flagm although probably an extra uop.
the inst count regression is on flagm, but we can't tolerate broken behaviour.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-18 15:26:47 -04:00
Paulo Matos e18a661b50 Refactor OP_STORESTACKMEM case in x87 Stack Opt Pass 2025-03-18 18:34:06 +01:00
Paulo Matos 16e5777816 Do not attempt direct encoding of 32bit addressing modes 
Fixes #4393
 2025-03-18 15:54:54 +01:00
Paulo Matos 64020e8828 Simplify by merging FSTF64 with FST 2025-03-18 15:54:54 +01:00
Ryan Houdek 929b111648 Merge pull request #4405 from Sonicadvance1/static_analysis_again 
Various: More static analysis warnings cleanup
 2025-03-17 13:08:11 -07:00
Ryan Houdek b901b42417 OpcodeDispatcher/X87: Optimize GPR moves using new IR operation 
This saves one instruction per FILD and FRSTOR
 2025-03-12 22:22:03 -07:00
Ryan Houdek 9f2f10a65f IR: Add new 128-bit vector move operation 
This allows us to slightly optimize some x87 behaviour.
 2025-03-12 22:21:28 -07:00
Ryan Houdek b0b41d00ee Various: More static analysis warnings cleanup 
NFC
 2025-03-12 17:27:41 -07:00
LC 10d34c9564 Merge pull request #4397 from Sonicadvance1/optimize_cas 
JIT: Optimize CAS
 2025-03-08 12:06:49 -05:00
Ryan Houdek a37d6a3841 JIT: Optimize CAS 
Hey kid, want to see a sick trick?

Finally optimal codegen for 64-bit cmpxchg.
 2025-03-07 14:24:45 -08:00
LC d5234a43da Merge pull request #4396 from Sonicadvance1/remove_old_comment 
AVX128: Remove old comment from VEXTRACT{F,I}128
 2025-03-07 17:20:23 -05:00
Ryan Houdek 2ae02ded74 AVX128: Remove old comment from VEXTRACT{F,I}128 
This comment isn't relevant anymore as unused half of ymm loads will get
DCE'd
 2025-03-07 12:00:35 -08:00
Ryan Houdek 031afbfb18 Various: Adds missing SPDX file headers 
NFC
 2025-03-07 11:34:31 -08:00
Ryan Houdek 0f5aff73ab Softfloat: Define INLINE 
This is embarassing. We were throwing away performance by failing to
use the softfloat library's inline helpers.

Turns out we needed to define `INLINE` to something in order for them to
work.

Feels bad.
 2025-03-07 01:56:13 -08:00
LC f0b208e692 Merge pull request #4391 from Sonicadvance1/optimize_vpalignr 
AVX128: Optimize vpalignr
 2025-03-07 02:11:18 -05:00
Ryan Houdek 4b36d4f1ea JIT: Fixe scalar reciprocal when AFP is supported 
Somehow I had completely missed this and recent reciprocal tests have
exposed it as a problem. When AFP is supported but not RPRES then we
were hitting this code path.

We were failing to insert in to the destination correctly, which because
the reciprocal is calculated using fdiv using a synthesized constant,
this would just zero the remaining portion of the register.
 2025-03-06 18:21:26 -08:00
Ryan Houdek 79ab76b42e AVX128: Optimize vpalignr 
When the shift size is exactly 16bytes, then it turns in to a move.

If the shift size is above 16-bytes then synthesize the zero register in
the OpcodeDispatcher, so the backend doesn't synthesize and not cache.
 2025-03-06 17:10:22 -08:00
Ryan Houdek 07afdca58b V{Load,Store}VectorMasked: Small offset support with ASIMD 2025-03-05 12:25:33 -08:00
Ryan Houdek 93ed346fd2 JIT: Optimize SVE offset VL loadstores 
This was only wired up for 256-bit SVE and wasn't ever hit for 128-bit
SVE. Ensure it works with 128-bit SVE, so mulvl needs to know when
128-bit is used. Then wire it up for vmaskmovps/pd. This saves one
instruction per operation.

Fixes #3791.
 2025-03-05 12:01:50 -08:00
Ryan Houdek 2bf87ff40f Various: Removes warnings about uninitialized variables 
NFC. These wouldn't even occur in practice.
 2025-03-04 19:59:26 -08:00
Ryan Houdek 81434cd233 Merge pull request #4377 from bylaws/sidt 
Implement SIDT/LSL
 2025-03-04 17:10:32 -08:00
Ryan Houdek b7f58e68c5 Merge pull request #4363 from pmatos/ReciprocalsFix 
Improve reciprocal estimate and tests
 2025-03-01 00:58:45 -08:00
Billy Laws 6ba2accbdc Frontend: Mark INVLPG as permission-restricted 2025-02-28 16:22:47 +00:00
Billy Laws 29ee94d331 Frontend: Correct TYPE_SECOND_GROUP_MODRM handling 2025-02-28 16:02:24 +00:00