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Code Issues Packages Projects Releases 67 Wiki Activity
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ff2c2f1e1f8ddc8da2a4f6151646725a3f0f9504
Commit Graph
2318 Commits
Author SHA1 Message Date
Lioncache ff2c2f1e1f Addressing: Remove unnecessary assert in LoadEffectiveAddress() 
ilog2 already has an assert for this.
 2025-03-28 06:08:08 -04:00
Lioncache 54dbb9f248 OpcodeDispatcher: Fix potential for uninitialized value use in RCRSmallerOp() 
If Src isn't a constant, then no value is actually assigned to SrcConst, so this
can result in uninitialized arithmetic being performed
 2025-03-28 04:45:40 -04:00
Ryan Houdek 21233430aa Merge pull request #4446 from lioncash/cond 
OpcodeDispatcher: Remove unnecessary 128-bit check in VPGATHER()
 2025-03-27 20:30:49 -07:00
Ryan Houdek bd1d6820b7 Merge pull request #4438 from Sonicadvance1/static_analysis_wars 
Static analysis warning fixes
 2025-03-27 20:30:37 -07:00
Lioncache 40b1c32008 OpcodeDispatcher: Remove unnecessary 128-bit check in VPGATHER() 
This is already guaranteed to be true, since it's checked in the outer if,
so this can just be a regular else statement.
 2025-03-27 23:08:59 -04:00
Ryan Houdek b5ed804578 Merge pull request #4444 from lioncash/jitcond 
JIT: Simplify SVE 256 operation asserts
 2025-03-27 19:46:23 -07:00
Ryan Houdek fbe3a86c4e Merge pull request #4443 from alyssarosenzweig/ra/cleanup 
RA: small cleanups
 2025-03-27 19:46:14 -07:00
Ryan Houdek ec976f3f75 Merge pull request #4435 from alyssarosenzweig/opt/pall-pf-af 
Pair PF/AF when spilling static regs
 2025-03-27 19:45:29 -07:00
Lioncache 35ee12e7e9 Addressing: Amend binary AND into logical AND in SelectAddressMode() 
Bitwise AND here is a little odd and was likely intended to be a logical AND.
 2025-03-27 17:29:08 -04:00
Lioncache 4497ab8844 JIT: Simplify SVE 256 operation asserts 
We can make these slightly less verbose.
 2025-03-27 16:55:20 -04:00
Alyssa Rosenzweig 9f399f3313 RegisterAllocationPass: rm unused arg to DecodeSRAReg 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-27 16:45:31 -04:00
Alyssa Rosenzweig 3939213336 RegisterAllocationPass: rm useless assertion 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-27 16:45:31 -04:00
Ryan Houdek b8165813b4 Merge pull request #4439 from pmatos/Init-SA 
Initialize class fields to null/zero
 2025-03-27 09:32:18 -07:00
Alyssa Rosenzweig cb91d585c3 Arm64Emitter: pair pf/af load/store 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-27 11:07:00 -04:00
Alyssa Rosenzweig 42ea711850 CoreState: squish and rearrange pf_raw/af_raw 
to allow next commit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-27 11:04:08 -04:00
Paulo Matos 4565f2b689 Initialize class fields to null/zero 
Silence a couple of static analyzer warnings.
 2025-03-27 15:35:40 +01:00
Alyssa Rosenzweig 2cfc42bd6a Arm64Emitter: simplify and fix !preserve_all regs 
stop doing weird special cases. just dump all the regs except what aapcs64 says
we don't have to.

this fixes saving x18 across thunks and things. so probably fixes things *cry*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-27 10:07:27 -04:00
Ryan Houdek 003de2b659 JIT: static analysis warnings 2025-03-27 04:36:41 -07:00
Ryan Houdek 4ab6c2252d IR: More validation for shifts 2025-03-27 04:36:41 -07:00
Ryan Houdek 8f9d818368 OpcodeDispathcer: static analysis warnings 2025-03-27 04:26:40 -07:00
Ryan Houdek 4ebc307744 IR: Ensure BFE ops can't try to extract element larger than size 2025-03-27 04:26:40 -07:00
Ryan Houdek 0b519b29d9 IR/IRDumper: static analysis warnings 2025-03-27 04:26:40 -07:00
Ryan Houdek 8881e8d96e IR/IREmitter: static analysis warnings 2025-03-27 04:26:40 -07:00
Ryan Houdek 9a99608f68 Passes/ConstProp: static analysis warnings 2025-03-27 04:26:40 -07:00
Alyssa Rosenzweig 7c42c7798c Arm64Emitter: fix a bunch of preserve_all 
* x18 wasn't getting spilled even though it was supposed to be.
* arm64ec preserve_all definitions were all messed up, specialize these to fix.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-26 16:47:39 -04:00
Ryan Houdek ab9123a427 JIT: Fix typo in VSha256U1 2025-03-25 18:19:37 -07:00
Ryan Houdek e504a8c979 Merge pull request #4428 from alyssarosenzweig/opt/vbsl-tie 
Tie VBSL source
 2025-03-25 16:09:17 -07:00
Alyssa Rosenzweig f87edbe1cb JIT: eliminate a zext in bfi 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-25 17:36:59 -04:00
Alyssa Rosenzweig 694e674fe6 IR: tie VExtr 
needed for sve-256 move reduction.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-25 15:22:55 -04:00
Alyssa Rosenzweig 7ebc0f32b8 IR: tie VInsGPR 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-25 15:16:25 -04:00
Alyssa Rosenzweig 68cacc2fc3 IR: tie VFMin/VFMax 
this was missed.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-25 15:16:25 -04:00
Alyssa Rosenzweig 43eb597044 IR: tie VBSL source 
this was missed before, noticed while experimenting with round robin RA.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-25 14:14:21 -04:00
Tony Wasserka 7efd827e78 Merge pull request #4378 from bylaws/volmd 
Implement PE volatile metadata support
 2025-03-25 10:23:53 +01:00
Ryan Houdek 2f6f8b93e9 Merge pull request #4424 from Sonicadvance1/converted_options 
Convert config options once
 2025-03-24 19:49:32 -07:00
Ryan Houdek d48413cbec Merge pull request #4426 from alyssarosenzweig/opt/shld-improvements 
Drop some masking in shld
 2025-03-24 19:24:51 -07:00
Billy Laws 51281f6a3a ARM64EC: Load volatile metadata 2025-03-24 22:01:49 +00:00
Billy Laws 7a5e08c5ab FEXCore: Use TSO range information when emitting IR 2025-03-24 22:01:49 +00:00
Billy Laws 642903a7bf FEXCore: Support tracking TSO range information 2025-03-24 22:01:49 +00:00
Alyssa Rosenzweig b86cbda03d OpcodeDispatcher: drop useless mask in trivial cmpxchg 
hit by upcoming opt pass, but we don't want to depend on that pass for that.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-24 16:17:04 -04:00
Alyssa Rosenzweig e26b9b12fa OpcodeDispatcher: drop useless zext in shld 
this gets deleted by an upcoming opt pass, but we shouldn't be depending on
the opt pass for it!

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-24 16:00:24 -04:00
Ryan Houdek 9bf47b3f23 Convert config options once 
Instead of keeping the vlaue as a string array in the MetaLayer, convert
the value to its final type once.

Improves performance in some hotpaths that were doing config based
string conversion in a relatively high frequency.
 2025-03-22 17:32:10 -07:00
Ryan Houdek 9a92f6f743 FEXCore: Remove CPUID option for SHA 
Instead use the HostFeatures option that exists which is controlled by
the {enable,disable}crypto option.
 2025-03-21 19:43:38 -07:00
Ryan Houdek ab7f6484cf Merge pull request #4414 from pmatos/AddrMode-DeusEx 
Fix address modes calculation on 32bit guests
 2025-03-20 13:21:53 -07:00
Paulo Matos b18f148575 Abstract AddressMode into its own header 
Also refactor usage of utility functions into x87 Stack Optimization Pass.
 2025-03-20 11:41:26 +01:00
Alyssa Rosenzweig 61d2a09827 OpcodeDispatcher: fix BT flags 
ZF needs to be preserved.

the new code is the same instr count on flagm although probably an extra uop.
the inst count regression is on flagm, but we can't tolerate broken behaviour.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-18 15:26:47 -04:00
Paulo Matos e18a661b50 Refactor OP_STORESTACKMEM case in x87 Stack Opt Pass 2025-03-18 18:34:06 +01:00
Paulo Matos 16e5777816 Do not attempt direct encoding of 32bit addressing modes 
Fixes #4393
 2025-03-18 15:54:54 +01:00
Paulo Matos 64020e8828 Simplify by merging FSTF64 with FST 2025-03-18 15:54:54 +01:00
Ryan Houdek 30798556fc Merge pull request #4415 from alyssarosenzweig/opt/avx-zero 
ConstProp: optimize StoreContext(128-bit zero)
 2025-03-17 14:02:06 -07:00
Alyssa Rosenzweig bc87c3d494 ConstProp: optimize StoreContext(128-bit zero) 
Turn this into stp to save a move in a /ton/ of AVX-128 code. It's pretty
annoying to optimize this at the dispatcher level because of the SRA cache, so
doing it in the ConstProp is a nice compromise solution.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-17 16:49:05 -04:00