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Code Issues Packages Projects Releases 67 Wiki Activity
143 Commits 11 Branches 71 Tags
fc0ce3d1dc14100dc8cf68ade405be4ece68115e
Commit Graph
80 Commits
Author SHA1 Message Date
Ryan Houdek fc0ce3d1dc Adds new IR ops to the AArch64 JIT 2020-03-06 07:56:02 +02:00
Ryan Houdek e9d1ec6aff Adds new IR ops to the interpreter 2020-03-06 07:56:02 +02:00
Ryan Houdek 6b636c3c26 Fixes a couple of instructions in the x86Tables 2020-03-06 07:56:02 +02:00
Ryan Houdek 2f5e2ea066 Fixes LODS and SCAS x86Table flags 2020-03-06 07:56:02 +02:00
Ryan Houdek 3bb9197e6a Adds VAND IR Op 2020-03-06 07:56:02 +02:00
Ryan Houdek a858296ecd Removes SSE41, SSE42, and AVX support from CPUID 2020-03-06 07:56:01 +02:00
Scott Mansell 2babc1292c GdbServer: Breakpoint intergation 2020-03-06 07:56:01 +02:00
Scott Mansell 9a89741ff2 gdbServer: Allow continuing 2020-03-06 07:56:01 +02:00
Scott Mansell e050eace1d Refactor context start/pause/step interface 2020-03-06 07:56:01 +02:00
Scott Mansell 545b542f9b GdbServer: Implement xml target for register order 
We can now simply memcpy much of memory state.
 2020-03-06 07:56:01 +02:00
Scott Mansell e44b3ca495 Gdbserver: Implement enough to reach gdb prompt 
Memory is implemented, but without any checking or
invalidation.
Registers just hardcode a RIP for my test elf.

But GDB can read the elf over tcp, initilize and allow you to create breakpoints, which get
writen back before continue (which is not hooked up)
 2020-03-06 07:56:01 +02:00
Scott Mansell 17ffe5a7b2 GdbServer: Support a few more packets 2020-03-06 07:56:01 +02:00
Scott Mansell 23db0f66ec Add a skeleton of a GdbServer 2020-03-06 07:56:01 +02:00
Ryan Houdek e0e708a9c0 Fixes three instructions necessary for shared apps to run 
Fixes MOVHPD which was failing.
Fixes FXSTOR and FXSAVE which was accidently loading the memory location
rather than doing an LEA of the address.
 2020-03-06 07:56:01 +02:00
Ryan Houdek e9be5430b9 Adds a couple new IR ops for easy movement of registers between classes. 2020-03-06 07:56:01 +02:00
Ryan Houdek af5a562508 Fixes bug in STOS and CMPS 
We were storing one too many elements. So even if the counter register
was zero it would do a store or comparison
 2020-03-06 07:56:00 +02:00
Scott Mansell 8a6efad301 Stub FNSTCW/FLDCW so libc.so.6 can be loaded 
Apparently doesn't need any other x86 instructions.
Or anything more than noped out state save/restore.
 2020-03-06 07:56:00 +02:00
Ryan Houdek 3f06f3e87d Fixes bug in PUSH op with RSP source. 
We were modifying RSP to adjust the stack first.
Then if the source used RSP then it was offset by the store size.

`push [rsp]` was broken before this
 2020-03-06 07:56:00 +02:00
Ryan Houdek 2df55d303a Fixes bug in SHR op 
Smaller ops could have been shifting data from the larger source in to
the smaller op space when it should have been zero'd
 2020-03-06 07:55:59 +02:00
Ryan Houdek 7a4d0fbfd3 Fixes bug in 64bit def mod instructions that are in 16bit mode 
These would have been forced to 64bit when they would have wanted to be
operating in 16bit mode.
Fixes that.
 2020-03-06 07:55:59 +02:00
Ryan Houdek afdbd9ebdc Fixes issues with PSLLDQ and PSRLDQ 
These are whole vector shift instructions and they shift by bytes rather
than bits.
You only get an immediate offset for the instruction.
Implements two new IR ops to account for these instructions

This also doesn't match AArch64 behaviour 100%, requires two
instructions to emulate rather than the single one on the x86-side
 2020-03-06 07:55:59 +02:00
Ryan Houdek af6eefb495 Fixes crash in IR Interpreter that can occur with large functions 
If the tmp space grew too large and had to resize then we would have
stale pointers.
Keep around the offset instead so we don't store invalid pointers.
 2020-03-06 07:55:59 +02:00
Ryan Houdek 3568cdb03b Adds VBITCast to IR Interpreter 2020-03-06 07:55:59 +02:00
Ryan Houdek 33ebeef246 Fixes IR Interpreter 
Updates it to support the IR style and branching requirements.
 2020-03-06 07:55:59 +02:00
Ryan Houdek bc294164e3 Updates project to allow it to be installed 
Installs as both a static library and a shared library
 2020-03-06 07:55:59 +02:00
Ryan Houdek 939e210a68 Updates SonicUtils 
Makes changes to match latest changes
 2020-03-06 07:55:54 +02:00
Ryan Houdek b58b5687e0 Fixes AArch64 custom ASM dispatcher 2020-03-06 07:55:46 +02:00
Ryan Houdek 6e72a365d9 Fixes for the AArch64 JIT 
Custom dispatcher isn't fully working yet, but fixes a few other bugs.
 2020-03-06 07:55:46 +02:00
Ryan Houdek cb81d0a1af Fixes CondJump on AArch64 JIT 2020-03-06 07:55:46 +02:00
Ryan Houdek efdf490c3c Adds support for ARM on the LLVM JIT 2020-03-06 07:55:46 +02:00
Scott Mansell 20fc6a489e Fix STOS to not load SSA regs across blocks 2020-03-06 07:55:45 +02:00
Ryan Houdek ee53b70bfe Actually enable LLVM optimization passes in the LLVM JIT 
We were using whatever was the LLVM default before.
 2020-03-06 07:55:45 +02:00
Ryan Houdek 9e132e107a Adds alignment information to the mem loadstore IR ops 
Allows us to not always emit unaligned loadstore ops for these
 2020-03-06 07:55:45 +02:00
Ryan Houdek f8b858e7fc Removes the EndFunction IR Op 2020-03-06 07:55:45 +02:00
Ryan Houdek db7b3d415d Adds VBitcast IR op 
Casts vector to a integer of the same width as the vector
 2020-03-06 07:55:44 +02:00
Ryan Houdek 3eb55d5f9f Fixes LLVM JIT with multiblock 2020-03-06 07:55:44 +02:00
Ryan Houdek 435357e06e Fixes a bug in STOS 2020-03-06 07:55:44 +02:00
Ryan Houdek 4e5d9452f7 Syscall doesn't end a block 2020-03-06 07:55:44 +02:00
Ryan Houdek a8d2cb4a9f Fixes LLVM JIT 
Doesn't yet work with multiblock
 2020-03-06 07:55:44 +02:00
Ryan Houdek 3a041c3b1c Fixes bug in block creation for any block containing RET. 
Would have a redundant StoreContext after the RET which broke IR
analysis
 2020-03-06 07:55:44 +02:00
Ryan Houdek e1cecbcfe3 Changes to the new multiblock frontend decoder 
Simple linear scan forward of instruction decoding isn't viable to do.
We need to break up the decoding at the block boundaries.
Otherwise our decoding gets in to the weeds and decodes trash.
 2020-03-06 07:55:37 +02:00
Ryan Houdek 5db8de625a Adds a few new instructions to the X86Tables 
I managed to hit these when messing with Multiblock.
 2020-03-06 07:55:37 +02:00
Ryan Houdek b7c7a34cf6 Changes (aggressively) how branching is handled in the frontend. 
This changes over CondJump to have a defined True and False branch path.
Additionally needing to change over everything to handle this.
This now means that a false branch condition will no longer assume
fallthrough past this instruction.
Currently the x86-64 JIT generates an additional jmp instruction on
fallthrough that isn't optimized away.

This is working towards improvements in our IR branching model and
improving IRValidation in doing so.
This is working towards the model that IRBlocks can only have 0-2
successors.
Ret/Exit - 0 successors
Jump - 2 successors
CondJump - 2 successors

TBD:
Syscall/CPUID - Breaking block?
 2020-03-06 07:55:37 +02:00
Ryan Houdek fc8c6c80fb Makes sure in Frontend we say that Entry and ConditionalJump fallthroughs are JumpTargets 2020-03-06 07:55:37 +02:00
Ryan Houdek 7da7880a41 Splits X86Table definitions in to multiple files 
Allows YouCompleteMe to handle these files and makes recompiling less of
a pain when one line is changed.
 2020-03-06 07:55:36 +02:00
Scott Mansell d1f2d85d0c Fix up usage tracking of Args. 
Make sure we keep them up to date when removing
nodes.
 2020-03-06 07:55:36 +02:00
Ryan Houdek 160240dc23 Adds a few AVX instructions to the X86Tables 2020-03-06 07:55:35 +02:00
Ryan Houdek 6890ae4e20 Adds an inblock time sampling routine to the x86-64 JIT 
Useful for a quick overview of the time spent in a function. It isn't
amazing for profiling since it effects the time in the function by
itself.
Only useful as a reference.
 2020-03-06 07:55:35 +02:00
Ryan Houdek 0a959475c5 Removes support for non-RA path on x86-64 JIT 
RA is now fully working, so this path is no longer necessary
 2020-03-06 07:55:35 +02:00
Ryan Houdek 668d392eb7 Adds support for spilling in the AArch64 JIT 2020-03-06 07:55:35 +02:00