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Code Issues Packages Projects Releases 67 Wiki Activity
1,401 Commits 11 Branches 71 Tags
fc093531c322cda5b26b6640ebf8da00a4d58edb
Commit Graph
527 Commits
Author SHA1 Message Date
Ryan Houdek fc093531c3 Fixes SHRD and SHRD by zero with 32bit source register 
This will still zext the GPR with zero shift, just won't update the
flags
 2020-09-28 16:58:26 -07:00
Ryan Houdek 912b6fb0f3 Merge pull request #442 from Sonicadvance1/ashr_fix 
Fixes smaller than 32bit ASHR
 2020-09-28 13:44:07 -07:00
Ryan Houdek f6c207b5c5 Fixes smaller than 32bit ASHR 
Need to operate on it as a 32bit value
 2020-09-27 23:11:58 -07:00
Ryan Houdek d404da1bf1 Fixes PSADBW in the opdispatcher 
Documentation in the x86 manuals implied operating at 8bit
 2020-09-27 16:53:50 -07:00
Ryan Houdek b0b3335178 Fixes VADDV in the x86_64 JIT 2020-09-27 16:53:25 -07:00
Ryan Houdek a919e532fc Merge pull request #437 from Sonicadvance1/ssse3 
Enables SSSE3 in CPUID
 2020-09-27 11:15:15 -07:00
Ryan Houdek 603580f291 Implements PHADDSW and PHSUBSW in the opdispatcher 
Both the MMX and XMM variants
 2020-09-27 11:08:21 -07:00
Ryan Houdek b409855605 Implements PMADDUBSW in the Opdispatcher 
This is some weirdly specific instruction
 2020-09-27 10:50:35 -07:00
Ryan Houdek 1c2f8dece5 Fixes typo in x86 VUXTL2 
This was supposed to shift right, not shift left
This IR op wasn't being used so it went unnoticed
 2020-09-27 10:38:46 -07:00
Ryan Houdek badc7f6562 Merge pull request #434 from Sonicadvance1/pmulhrsw 
Implements SSSE3 PMULHRSW
 2020-09-27 10:38:14 -07:00
Ryan Houdek 6b3e1bd75b Implements PHADD and PHSUB in the OpDispatcher 2020-09-27 10:32:10 -07:00
Ryan Houdek 72d0dd30a6 Fixes 8byte register VAddP in the x86 JIT 2020-09-27 10:31:35 -07:00
Ryan Houdek 4f73897a7f Fixes 8byte register VaddP on AArch64 JIT 2020-09-27 10:31:35 -07:00
Ryan Houdek afa4f0df38 Enables SSSE3 in CPUID 2020-09-26 20:40:22 -07:00
Ryan Houdek da16b40e12 Implements PMULHRSW in the opdispatcher 
Both the MMX and XMM versions
 2020-09-26 15:32:21 -07:00
Ryan Houdek 315e909ed0 Implements new VectorImm in the x86 JIT 2020-09-26 15:31:18 -07:00
Ryan Houdek b30e517a0b Implements new VectorImm op in the AArch64 JIT 2020-09-26 15:31:05 -07:00
Ryan Houdek 820c10b439 Implements new VectorImm op in the interpreter 2020-09-26 15:30:43 -07:00
Ryan Houdek 58425637e2 Implements pshufb in the opdispatcher 
This hits both the MMX and XMM variants
 2020-09-26 13:08:31 -07:00
Ryan Houdek 91229c8ea2 Implements new VTBL1 IR op in x86 JIT 2020-09-26 12:59:34 -07:00
Ryan Houdek 59bffc7431 Implements new VTBL1 instruction in AArch64 JIT 2020-09-26 12:59:34 -07:00
Ryan Houdek a5f6a5b26e Implements new VTBL1 op in the interpreter 2020-09-26 12:59:34 -07:00
Ryan Houdek 55077cfa55 Implements MMX register based palignr 
We had already implemented the XMM variant
 2020-09-26 12:53:51 -07:00
Ryan Houdek 9cdd0c4776 Fixes an edge case in our palignr implementation 
When the shift amount is greater than the size of both the registers
then it'll set the resulting register to zero
 2020-09-26 12:53:51 -07:00
Ryan Houdek 12a4dd6d2d Fixes VExtr in the ARM64 JIT for 8byte registers 
We only expected 16byte registers before
 2020-09-26 12:52:26 -07:00
Ryan Houdek bd37d007c9 Fixes 64bit register usage in VExtr on x86_64 
We would need to fall back to MMX if we wanted to handle that cleanly
there.
Just emulate instead of using MMX
 2020-09-26 12:52:26 -07:00
Ryan Houdek a11aed2f47 Removes some undefined behaviour in the interpreter VExtr implementation 2020-09-26 12:52:26 -07:00
Ryan Houdek ec06806244 Implements support for SSSE3 PABS{B,W,D} 
For both MMX and XMM registers
 2020-09-26 12:47:01 -07:00
Stefanos Kornilios Mitsis Poiitidis 83db01f505 Merge pull request #429 from Sonicadvance1/psign 
Implements support for SSSE3 PSIGN{B,W,D}
 2020-09-26 20:20:06 +03:00
Stefanos Kornilios Mitsis Poiitidis de62124b95 Merge pull request #428 from Sonicadvance1/lzcnt 
Implements ABM's LZCNT instruction
 2020-09-26 20:11:47 +03:00
Stefanos Kornilios Mitsis Poiitidis ca676e324d Merge pull request #427 from Sonicadvance1/duplicated_ops 
Implements the couple of duplicated ops
 2020-09-26 20:09:58 +03:00
Stefanos Kornilios Mitsis Poiitidis 5cb3a9df9d Merge pull request #426 from Sonicadvance1/addsub 
Implements ADDSUB{PS, PD}
 2020-09-26 20:09:48 +03:00
Stefanos Kornilios Mitsis Poiitidis cf6b07fc16 Merge pull request #425 from Sonicadvance1/remove_direct_widening_use 
Removes some direct usage of widening flag
 2020-09-26 20:09:35 +03:00
Stefanos Kornilios Mitsis Poiitidis 8662fb0db7 Merge pull request #424 from Sonicadvance1/mmx_cvt 
Implements missing mmx conversion ops
 2020-09-25 18:21:16 +03:00
Stefanos Kornilios Mitsis Poiitidis e145876898 Merge pull request #404 from Sonicadvance1/x87_bcd 
Adds support for BCD x87 intructions
 2020-09-25 18:07:49 +03:00
Ryan Houdek faa06771ef Implements support for SSSE3 PSIGN{B,W,D} 
For both MMX and XMM registers
 2020-09-24 19:45:39 -07:00
Ryan Houdek 7c73920a2c Implements the new IR ops in the x86-64 JIT 2020-09-24 19:44:55 -07:00
Ryan Houdek 6254d15f02 Implements the new IR ops in the ARM64 JIT 2020-09-24 19:36:15 -07:00
Ryan Houdek 2079e3ca31 Implements the new IR ops in the interpreter 2020-09-24 19:35:18 -07:00
Ryan Houdek 84936e6297 Implements ABM's LZCNT instruction 
This overlaps the previous BSR instruction which is why the table had to
be changed.

We were accidently claiming support for ABM in CPUID before so that
didn't need to be changed.

We now implement both LZCNT and TZCNT so we fully support ABM now.
 2020-09-23 22:35:32 -07:00
Ryan Houdek 697df88314 Implements the new CLZ IR op in the x86 JIT 2020-09-23 22:14:56 -07:00
Ryan Houdek 47c3fdafd7 Implements the new CLZ op in the ARM64 JIT 2020-09-23 22:14:36 -07:00
Ryan Houdek 935deb0167 Implements new CLZ op in the interpreter 2020-09-23 22:14:15 -07:00
Ryan Houdek c72d50a9c6 Implements the couple of duplicated ops 
SAL is exactly the same as SHL
TEST is exactly the same as the previous TESTs
Bit silly of encodings since compilers will never actually generate
these

No unit tests on these since getting nasm to emit it is a PITA
 2020-09-23 18:56:26 -07:00
Ryan Houdek ae3c38e9e5 Implements ADDSUB{PS, PD} in the OpDispatcher 2020-09-23 18:08:19 -07:00
Ryan Houdek e238afe2fb Removes some direct usage of widening flag 
Instead use our helpers to determine the sizes to stay consistent
 2020-09-23 17:30:43 -07:00
Ryan Houdek 35798c8d9d Implements missing mmx conversion ops 2020-09-23 17:21:01 -07:00
Ryan Houdek f5a7a3deec Fixes move with mem offset 
Move with mem offset defaults to 64bit offset and the literal size is
changed based on address size override rather than operand size
override.

Operand size override still works in this case, but only for the
register being passed in.
 2020-09-23 10:43:12 -07:00
Stefanos Kornilios Mitsis Poiitidis 6f58e1e1c5 Merge pull request #419 from Sonicadvance1/x87_fixes 
x87 fixes
 2020-09-23 20:19:29 +03:00
Ryan Houdek e395c37de6 Fixes flags calculation in CMPSB 
The order of these ops were flipped
 2020-09-23 10:00:18 -07:00