Alyssa Rosenzweig
fabd6be5af
OpcodeDispatcher: drop SUB defer
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-07-05 16:24:54 -04:00
Alyssa Rosenzweig
a38205069b
OpcodeDispatcher: fix SBB carry flag
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do it the naive way, just applying the x86 definitions of SBB.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-07-04 16:58:45 -04:00
Ryan Houdek
0d06e3e47d
Revert "OpcodeDispatcher: add cache"
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This reverts commit 46676ca376
2024-07-02 20:24:57 -07:00
Ryan Houdek
472a373861
Merge pull request #3786 from Sonicadvance1/non_temporal_stores
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OpcodeDispatcher: Implement support for non-temporal vector stores
2024-07-01 18:57:38 -07:00
Ryan Houdek
a451420911
Merge pull request #3783 from Sonicadvance1/optimize_vector_zeroregister
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OpcodeDispatcher: Optimize x86 canonical vector zero register
2024-07-01 18:57:31 -07:00
Ryan Houdek
babde31bf0
AVX128: Fixes vmovlhps
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We didn't have a unit test for this and we weren't implementing it at
all.
We treated it as vmovhps/vmovhpd accidentally. Once again caught by the
libaom Intrinsics unit tests.
2024-07-01 13:54:11 -07:00
Ryan Houdek
5821054d91
Merge pull request #3789 from Sonicadvance1/avx128_minor_pshufb_opt
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AVX128: Minor optimization to 256-bit vpshufb
2024-06-30 15:45:11 -07:00
Ryan Houdek
4626145374
Merge pull request #3792 from Sonicadvance1/avx128_fix_scalar_fma
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AVX128: Fixes scalar FMA accidentally using vector wide
2024-06-30 15:36:09 -07:00
Ryan Houdek
1393dc2a5b
AVX128: Fixes scalar FMA accidentally using vector wide
2024-06-30 14:36:33 -07:00
Ryan Houdek
cffae9cb0f
AVX128: Minor optimization to 256-bit vpshufb
2024-06-30 13:41:03 -07:00
Ryan Houdek
7d05610da7
OpcodeDispatcher: Optimize x86 canonical vector zero register
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The canonical way to generate a zero register vector in x86 is to xor
itself. Capture this can convert it to canonical zero register instead.
Can get zero-cycle renamed on latest CPUs.
2024-06-29 22:21:53 -07:00
Ryan Houdek
f4ff1b0688
OpcodeDispatcher: Implement support for non-temporal vector stores
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x86 doesn't have a lot of non-temporal vector stores but we do have a
few of them.
- MMX: MOVNTQ
- SSE2: MOVNTDQ, MOVNTPS, MOVNTPD
- AVX: VMOVNTDQ (128-bit & 256-bit), VMOVNTPD
Additionally SSE4a adds 32-bit and 64-bit scalar vector non-temporal
stores, which we keep as regular stores. Since ARM doesn't have matching
semantics for those.
Additionally SSE4.1 adds non-temporal vector LOADS which this doesn't
touch.
- SSE4.1: MOVNTDQA
- AVX: VMOVNTDQA (128-bit)
- AVX2: VMOVNTDQA (256-bit)
Fixes #3364
2024-06-29 22:05:56 -07:00
Ryan Houdek
ebfa65fedc
AVX128: Minor optimization to vmov{l,h}{ps,pd}
2024-06-29 19:27:16 -07:00
Ryan Houdek
aba7a3a830
AVX128: Fixes vblendps lower and upper selector
2024-06-27 17:20:39 -07:00
Ryan Houdek
9027d1eee7
AVX128: Fixes bug in vector immediate shift
2024-06-27 16:22:14 -07:00
Alyssa Rosenzweig
f9b53c6b51
AVX_128: save a move in vzeroall
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-06-27 10:30:25 -04:00
Ryan Houdek
4d56fec5f1
AVX128: Work around glibc fault testing
2024-06-26 16:49:00 -07:00
Ryan Houdek
975069825e
AVX128: Fix a real bug with VCVTPS2PH
2024-06-26 16:49:00 -07:00
Mai
a031a49546
Merge pull request #3767 from Sonicadvance1/avx128_fix_wide_shift
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AVX128: Fixes wide shifts
2024-06-26 17:29:09 -04:00
Ryan Houdek
f277025c9a
AVX128: Fixes wide shifts
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During refactoring this was missed and rerunning unittests locally
caught it. 256-bit operations get their shift only from the lower half
of the vector register.
2024-06-26 14:16:39 -07:00
Ryan Houdek
3a89df9bed
AVX128: Implement support for F16C
2024-06-26 14:05:12 -07:00
Ryan Houdek
f6a0866fbb
IR: Split Vector_FToF2 in to VFCVTL2 and VCVTFN2
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I forgot in the narrowing case we need to be careful about insert. No IR
op used Vector_FToF2 with narrowing.
2024-06-26 14:03:41 -07:00
Ryan Houdek
756fa2ecc5
Merge pull request #3766 from alyssarosenzweig/opt/f16c-round
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Optimize vcvtps2ph
2024-06-26 14:03:24 -07:00
Alyssa Rosenzweig
d2324f4a93
OpcodeDispatcher: optimize vcvtps2ph
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We can avoid a LOT of pointless work with some dedicated IR ops for specifically
overriding the round mode.
Small behaviour change here: we no longer reset FTZ. I think this is a bug fix?
But if it's not it's not hard to fix.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-06-26 16:46:21 -04:00
Ryan Houdek
a4fa3a460e
OpcodeDispatcher: Implement AVX gathers with SVE256
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Just to ensure we still have feature parity.
2024-06-26 16:00:53 -04:00
Ryan Houdek
77ba708933
AVX128: Implement support for gather load instructions
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This is the last family of instructions that we needed to implement for
AVX2 to be properly advertised!
2024-06-26 16:00:53 -04:00
Alyssa Rosenzweig
d1d41f5645
Merge pull request #3763 from alyssarosenzweig/rclse/less-aggressive
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Remove RCLSE
2024-06-26 15:14:14 -04:00
Ryan Houdek
94fd100fc7
Merge pull request #3719 from lioncash/f16c
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OpcodeDispatcher: Handle F16C operations
2024-06-26 12:12:13 -07:00
Lioncache
cd5a809ec9
OpcodeDispatcher: Handle VCVTPS2PH
2024-06-26 15:05:03 -04:00
Lioncache
045a8efbeb
OpcodeDispatcher: Handle VCVTPH2PS
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Fairly straightforward, since we already have handling for half-float conversions.
2024-06-26 15:05:00 -04:00
Alyssa Rosenzweig
46676ca376
OpcodeDispatcher: add cache
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-06-26 14:49:05 -04:00
Ryan Houdek
832b247fc1
SVE258: Implement support for FMA3
2024-06-25 11:24:46 -07:00
Ryan Houdek
0e8b53d566
AVX128: Implement FMA3 instructions
2024-06-25 11:23:50 -07:00
Ryan Houdek
41923bac99
OpcodeDispatcher: Fixes PCMUL with weird selectors and zero-extend
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We had a bug where we weren't correctly ignoring the non-used bits in
the selector. This was causing an assert in the ARM backend.
2024-06-25 12:54:03 -04:00
Alyssa Rosenzweig
c6148f6bf1
AVX128: fix VPCLMULQDQl
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use the helper. I assumed the lack of zero extension here was intentional.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-06-25 12:51:21 -04:00
Alyssa Rosenzweig
77aaa9af4d
Merge pull request #3748 from Sonicadvance1/avx_15
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AVX128: More instructions Part 4
2024-06-25 12:39:48 -04:00
Ryan Houdek
7069643ae6
AVX128: Implement support for VPCLMULQDQ
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This is just the 128-bit version twice.
2024-06-25 10:03:33 -04:00
Ryan Houdek
34272fc134
AVX128: Implement support for vperm{d,ps}!
2024-06-25 10:03:33 -04:00
Ryan Houdek
1d41002dfe
AVX128: Implement support for variable vpermil{ps,pd}
2024-06-25 10:03:33 -04:00
Ryan Houdek
563bf342d5
AVX128: Implement support for vptest
2024-06-25 10:03:33 -04:00
Ryan Houdek
efd5fabb95
AVX128: Implement support for vtest{ps,pd}
2024-06-25 10:03:33 -04:00
Ryan Houdek
c1da525110
AVX128: Implement support for vperm2{f128,i128}
2024-06-25 10:03:33 -04:00
Ryan Houdek
5ce6c88a88
AVX128: Reenable {ldm,stm}mxcsr. Can use the regular implementation.
2024-06-25 10:03:33 -04:00
Ryan Houdek
64cce7c6fa
AVX128: Implement support for xsave/xrstor
2024-06-25 10:03:33 -04:00
Ryan Houdek
4544e5b51f
AVX128: Implement support for vblend{ps,pd}/vpblendvb
2024-06-25 10:03:33 -04:00
Ryan Houdek
eb3e314946
AVX128: Implement support for vmaskmovdqu
2024-06-25 10:03:33 -04:00
Ryan Houdek
8b65c3de10
AVX128: Implement vmaskmov{ps,pd}, vpmaskmov{d,q} using SVE2 gather loadstores.
2024-06-25 10:03:33 -04:00
Ryan Houdek
c2beb27a9d
AVX128: Implement support for vpalignr
2024-06-25 10:03:33 -04:00
Ryan Houdek
05fdec9e72
AVX128: Implement support for vmpsadbw
2024-06-25 10:03:33 -04:00
Ryan Houdek
e8e3c95349
AVX128: Implement support for vpsadbw
2024-06-25 10:03:33 -04:00
Alyssa Rosenzweig