Commit Graph
690 Commits
Author SHA1 Message Date
Stefanos Kornilios Mitsis Poiitidis fa35e79c3f arm64: Fix lr pushing 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis bcf382afc4 Interpreter: Fix LSHR to correctly zero extend 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis 193a72aa56 SRA: Address review feedback 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis 94fb009f4b SRA: Address review feedback 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis 5fd77f8228 arm64: Fix FPR spilling 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis 41285865ba arm64: Fix asserts 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis c95d40e9be arm64: Spill/Fill static ra around OP_SYSCALL 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis 82545796b8 static-ra: Use LogMan::* instead of assert/printf 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis 2ed8163a98 arm64: Cleanup & optimize Static and Dynamic spills on call 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis 30d7c02b60 arm64: Really fix Popcount to take into account opsize 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis 20a9b93019 OpDisp: Fix CondJUMPRCXOp 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis 76367f0afc arm64: Remove some debug logic 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis c20b27965d arm64: Fix Popcount to take into account opsize 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis 6e053f0055 arm64: Fix IsGPR && IsFPR for SRA 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis 80d1766bf0 arm64: Correctly handle signal and SRA interactions 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis a1f7c7da55 arm64: Fix Exit handler calling from signal 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis de0ed19e86 Arm64: Fix build for CreateRegPair 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis cdb2075522 X64: Fix RegisterClasses Count 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis 204fda62f1 IR: Fix CreateElementPair edge cases, Remove Load/StoreContextPair 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis fbe87101db IR: Remove Load/StoreContextPair 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis 17dc0bfcd8 SRA: Only do read-alias if accessing low part of register 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis c67aa0b83d OpDisp: Don't use LoadContextPair, it is kludgy and breaks SRA 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis 9c5a1fd5ea SRA: Static Register Allocation, arm64 only 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis f724392ef8 Merge pull request #601 from Sonicadvance1/fix_cvtsi2ss_64bit
Adds support for proper sized GPR->FPR sized conversions
2021-01-05 12:03:33 +02:00
Ryan Houdek 4907bda639 Adds support for proper sized GPR->FPR sized conversions
Both x86 and AArch64 support converting from one sized GPR to another
sized FPR. Expose it in our IR op.

Fixes a bug in CVTSI2SS with a 64bit source and it was treating the
input source as a 32bit value.

eg:
0x0000'0000'FFFF'FFFF was treated as converting to -1 float, which was wrong since it is a 64bit value
2020-12-30 10:07:12 -08:00
Ryan Houdek 8bd76885ea Implements the rest of the prefetch ops and nops
Prefetch is highly architecture specific and a lot of these don't
actually map 1:1 with AArch64 anyway.
Just nop out
2020-12-27 19:10:41 -08:00
Ryan Houdek 69de873c34 Fixes some tables definitions for 32bit 2020-12-19 19:33:28 -08:00
Ryan Houdek 37983006f0 Moves FEXCore's SignalDelegator and SyscallHandler to the frontend
Sadly these things can't be split without breaking functionality so it
turns in to a bit of a mess.

SyscallHandler is very much something that is a Linux only construct and
shouldn't be in FEXCore itself. Lets the frontend register a
Syscallhandler with FEXCore. FEXCore itself is then aware of the current
syscall ABI and handles the ABI in an optimal fashion.
So it is not a 100% clean break otherwise we would lose performance.

The SignalDelegator then needs to move to the frontend since the
SyscallHandler requires it for signal based syscalls.
The CPU backend signal handling still needs to happen in FEXCore because
it is a very tight coupling with the CPU backend.
Once we need to support more Signal handling we can give the backends
cleaner support to select which specific OS handler to handle.
2020-12-13 22:38:04 -08:00
Ryan Houdek 36b24ad141 Removes all uses of non-unified memory and SHM regions
Let's just delete the whole thing!
2020-12-10 02:09:52 -08:00
Ryan Houdek 899e24abd0 Removes non-unified memory path from Interpreter 2020-12-10 02:01:14 -08:00
Ryan Houdek dc8caeaf91 Removes non-unified memory path from x86_64 2020-12-10 02:01:14 -08:00
Ryan Houdek 8e3ac44e65 Removes non-unified memory path from ARM64 2020-12-10 02:01:14 -08:00
Ryan Houdek 20a93ba96c Makes us handle DFL smarter
For the ones that should be IGNORE we can safely ignore them at that
point.
For the ones that have a default behaviour of crashing, just go ahead
and crash.

This was having the fun problem space that if we received an ignore
event, we would remove the fault handler then if the guest registered a
handler it would have never been called.

SIGWINCH specifically is one that defaults to ignore and we need to care
about. If SIGWICH happened before the guest registered a handler then it
would never receive the signal.

The ones that their default behaviour is faulting are fine to uninstall
and then immediately crash, since it is a real crash at that point.
2020-12-09 20:07:03 -08:00
Ryan Houdek 30dc9128ca Removes the last usage of 8bit and 16bit multiply
This was causing issues in 32bit xeyes.
A couple of the multiply ops were still using 8bit and 16bit multiply
while the other one was already sexting or zexting the source.
2020-12-04 08:59:52 -08:00
Stefanos Kornilios Mitsis Poiitidis b2b0d9318a arm64: Fix OP_SELECT & OP_CONDJUMP gpr/fpr detection 2020-12-04 16:04:27 +02:00
Stefanos Kornilios Mitsis Poiitidis 1363be8239 x64: Add support for floats in OP_SELECT & OP_CONDJUMP 2020-12-04 15:30:55 +02:00
Stefanos Kornilios Mitsis Poiitidis b32ed1db8c x64: Refactor CC logic, add float compares 2020-12-04 15:30:55 +02:00
Stefanos Kornilios Mitsis Poiitidis b044413952 OpDisp, IR, Backends: Add Float compares to Select, CondJump, COND_F* 2020-12-04 15:30:55 +02:00
Stefanos Kornilios Mitsis Poiitidis cfdf6ebf6b IR: Change FCMP to return x86-style flags 2020-12-04 08:55:19 +02:00
Stefanos Kornilios Mitsis Poiitidis 003991e495 Merge pull request #503 from Sonicadvance1/remove_duplicate_compaction
Remove duplicated compaction pass
2020-12-04 08:44:21 +02:00
Ryan Houdek c116a20e13 Merge pull request #542 from FEX-Emu/skmp/frontend-improve-reps
OpDisp: Read DF outside REP loops as it won't change
2020-12-03 20:23:40 -08:00
Ryan Houdek 439d49b802 Merge pull request #550 from FEX-Emu/skmp/improve-dead-flags
DFSE: Fix dead clag calculation, Extend InvalidateFlags
2020-12-03 20:18:43 -08:00
Ryan Houdek c7c2e56ae5 Merge pull request #552 from FEX-Emu/skmp/perblock-debug-data
JITSYMS: Per-block symbol information
2020-12-03 20:13:34 -08:00
Ryan Houdek 4187123b49 Merge pull request #551 from FEX-Emu/skmp/arm64-backend-opts
arm64: Backend Opts
2020-12-03 20:08:53 -08:00
Ryan Houdek eb57f5f489 Merge pull request #547 from FEX-Emu/skmp/optimize-flag-access
IR: Move BFEs to SetFlag, remove from OP_STOREFLAG
2020-12-03 20:07:53 -08:00
Ryan Houdek 12237abf67 Merge pull request #543 from FEX-Emu/skmp/frontend-improve-ss-sd
frontend: Improve IR for some *SS/*SD opcodes
2020-12-03 20:06:47 -08:00
Ryan Houdek 17402aa02d Remove duplicated compaction pass
RA Pass and passmanager compaction pass don't need to be independent.
This saves some memory.

In the future we should allow passes to fetch passes by name, that will
be part of the PassManager improvement in the future
2020-12-03 19:58:47 -08:00
Stefanos Kornilios Mitsis Poiitidis 62a5bc457d OpDisp: Read DF outside REP loops as it won't change 2020-12-03 20:19:00 +02:00
Stefanos Kornilios Mitsis Poiitidis b2d862a8c7 IR: Replace Sext with Sbfe 2020-12-03 20:08:08 +02:00
Stefanos Kornilios Mitsis Poiitidis bc5b235b7c CompileService: Fix DebugData 2020-12-03 18:58:58 +02:00