lioncash
f5a337a142
OpcodeDispatcher: Handle VSUBPD
2022-12-12 21:09:53 +00:00
lioncash
2b9d0314ce
OpcodeDispatcher: Handle VSUBPS
2022-12-12 21:05:30 +00:00
Ryan Houdek
293734408c
Merge pull request #2225 from lioncash/rcps
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OpcodeDispatcher: Handle VRCPPS/VRCPSS
2022-12-12 12:04:46 -08:00
lioncash
39f0c8542f
OpcodeDispatcher: Handle VRCPSS
2022-12-12 19:48:21 +00:00
lioncash
6877d5b3ec
OpcodeDispatcher: Handle VRCPPS
2022-12-12 19:48:21 +00:00
lioncash
a6c30b35dc
OpcodeDispatcher: Handle VLDDQU
2022-12-12 19:41:29 +00:00
lioncash
fa0ff71ddf
OpcodeDispatcher: Handle VPABSD
2022-12-12 18:47:10 +00:00
lioncash
c91ccf2cbe
OpcodeDispatcher: Handle VPABSW
2022-12-12 18:47:10 +00:00
lioncash
41df5f816d
OpcodeDispatcher: Handle VPABSB
2022-12-12 18:47:10 +00:00
lioncash
36a6264571
OpcodeDispatcher: Handle VPCMPEQQ
2022-12-12 18:00:38 +00:00
lioncash
12f01bc93a
OpcodeDispatcher: Handle VPCMPEQD
2022-12-12 17:55:07 +00:00
lioncash
777b2c7966
OpcodeDispatcher: Handle VPCMPEQW
2022-12-12 17:51:36 +00:00
lioncash
f0141f124d
OpcodeDispatcher: Handle VPCMPEQB
2022-12-12 17:42:29 +00:00
lioncash
283b178285
OpcodeDispatcher: Handle VPCMPGTQ
2022-12-12 17:29:36 +00:00
lioncash
d3a5eef08a
OpcodeDispatcher: Handle VPCMPGTD
2022-12-12 17:13:46 +00:00
lioncash
1bac33ff44
OpcodeDispatcher: Handle VPCMPGTW
2022-12-12 17:13:46 +00:00
lioncash
327a6f52fd
OpcodeDispatcher: Handle VPCMPGTB
2022-12-12 17:13:46 +00:00
Ryan Houdek
4f313f5d40
Merge pull request #2219 from Sonicadvance1/handle_pf_write
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Dispatcher: Calculate REG_ERR correctly using ARM ESR_EL1
2022-12-12 09:02:27 -08:00
Ryan Houdek
b42b4e03a4
Merge pull request #2218 from Sonicadvance1/GOT_optimization
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OpCodeDispatcher: Optimize a case of GOT calculation
2022-12-12 09:02:18 -08:00
Ryan Houdek
ab14375a03
Merge pull request #2222 from lioncash/rsqrt
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OpcodeDispatcher: Handle VRSQRTSS/VRSQRTPS
2022-12-12 09:02:04 -08:00
lioncash
c4c93f5bfe
OpcodeDispatcher: Handle VRSQRTSS
2022-12-12 16:30:34 +00:00
lioncash
3504ba068e
OpcodeDispatcher: Handle VRSQRTPS
2022-12-12 16:11:16 +00:00
lioncash
88b88c9cd3
OpcodeDispatcher: Handle VBROADCASTI128
2022-12-12 15:51:12 +00:00
lioncash
e99928990e
OpcodeDispatcher: Handle VPBROADCASTQ
2022-12-12 15:41:41 +00:00
lioncash
6733f83471
OpcodeDispatcher: Handle VPBROADCASTD
2022-12-12 15:37:59 +00:00
lioncash
a14cce27a4
OpcodeDispatcher: Handle VPBROADCASTW
2022-12-12 15:34:17 +00:00
lioncash
04d5b53389
OpcodeDispatcher: Handle VPBROADCASTB
2022-12-12 15:31:17 +00:00
Ryan Houdek
a6b0181cd4
OpCodeDispatcher: Optimize a case of GOT calculation
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32-bit GOT calculation needs to do a call+pop to do get the EIP on
32-bit. LEA doesn't work because it there is no EIP relative ops like on
x86-64.
This causes a terrible block split on every GOT calculation without the
optimization in place.
Now the block can continue through this weird GOT calculation.
This will be worthwhile for our 32-bit thunks where for some reason the
GOT calculation can't be removed. The GOT is calculated even though it
isn't used.
2022-12-10 02:50:48 -08:00
Ryan Houdek
82ad26307c
Dispatcher: Calculate REG_ERR correctly using ARM ESR_EL1
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On Fault then ARM will return information about the fault in ESR_EL1 to
the user.
We need to decode what ESR_EL1 means in the context of the fault to get
the flags we care about.
The flags we care about specifically are PF_USER and PF_WRITE.
PF_PROT would have been interesting but I didn't see when this gets
returned to the user. ARM makes the difference if the page is unmapped
or "mapped" with PROT_NONE. x86 doesn't make the distinction here.
This should fix an issue that a user was hitting.
2022-12-09 15:44:11 -08:00
lioncash
b891999a7f
OpcodeDispatcher: Handle VBROADCASTF128
2022-12-08 03:18:58 +00:00
lioncash
a53fd07bda
OpcodeDispatcher: Handle VBROADCASTSD
2022-12-08 02:58:12 +00:00
lioncash
8f213b75be
OpcodeDispatcher: Handle VBROADCASTSS
2022-12-08 02:40:36 +00:00
Ryan Houdek
b73aeb8902
Merge pull request #2214 from lioncash/stmxcsr
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OpcodeDispatcher: Handle VLDMXCSR/VSTMXCSR
2022-12-07 17:07:07 -08:00
lioncash
d642c1a646
OpcodeDispatcher: Handle VLDMXCSR/VSTMXCSR
2022-12-08 00:42:13 +00:00
lioncash
e42de0b645
OpcodeDispatcher: Handle VSQRTSD
2022-12-07 22:42:16 +00:00
lioncash
9ef5247dd7
OpcodeDispatcher: Handle VSQRTSS
2022-12-07 22:42:16 +00:00
lioncash
25428cb28c
OpcodeDispatcher: Handle VSQRTPD
2022-12-07 22:42:16 +00:00
lioncash
2125949d6d
OpcodeDispatcher: Handle VSQRTPS
2022-12-07 22:42:16 +00:00
Ryan Houdek
7ac21e794d
Merge pull request #2212 from lioncash/comiss
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OpcodeDispatcher: Handle VCOMISD/VCOMISS/VUCOMISD/VUCOMISS
2022-12-07 14:38:49 -08:00
lioncash
4aa0f3d0a4
OpcodeDispatcher: Handle VCOMISD
2022-12-07 22:06:25 +00:00
lioncash
740c983f65
OpcodeDispatcher: Handle VCOMISS
2022-12-07 22:06:25 +00:00
lioncash
83bccc0032
OpcodeDispatcher: Handle VUCOMISD
2022-12-07 22:06:22 +00:00
lioncash
d1ab636df1
OpcodeDispatcher: Handle VUCOMISS
2022-12-07 21:22:19 +00:00
lioncash
26b629833e
OpcodeDispatcher: Handle VPAVGW
2022-12-07 21:07:43 +00:00
lioncash
95964f8dd8
OpcodeDispatcher: Handle VPAVGB
2022-12-07 21:07:40 +00:00
Ryan Houdek
94ae2e3a9c
Merge pull request #2209 from lioncash/ins
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IR: Handle 128-bit VInsElement with SVE
2022-12-07 11:08:47 -08:00
lioncash
eae33b0c50
IR: Handle 128-bit VInsElement with SVE
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Currently VDupElement allows duplicating 128-bit elements in 256-bit
vectors with SVE, so we can extend VInsElement to have similar behavior.
2022-12-07 18:41:45 +00:00
Ryan Houdek
e9aa368a62
Merge pull request #2208 from lioncash/zero
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OpcodeDispatcher: Explicitly zero upper lanes
2022-12-07 10:13:53 -08:00
lioncash
5a37786da7
OpcodeDispatcher: Explicitly zero upper lanes
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Makes our intent to zero-extend the upper lanes explicit and lets us
remove a special case in the LoadSource implementation.
This also makes things a little nicer since we're not hardcoding 32 byte
stores.
2022-12-07 17:22:20 +00:00
lioncash
4cf3805950
OpcodeDispatcher: Handle VADDSD
2022-12-07 16:43:47 +00:00
lioncash