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653 Commits
Author SHA1 Message Date
LC d5db2ccf18 Merge pull request #4475 from Sonicadvance1/x87_stack_bug 
x87OptimizationPass: Fixes {Inc,Dec}StackPop
 2025-04-03 11:25:53 -04:00
Ryan Houdek cebcf50c65 x87OptimizationPass: Fixes {Inc,Dec}StackPop 
On the slow path these were pushing and popping in the wrong direction.
Switch them around to ensure the unittests work.
 2025-04-02 14:25:02 -07:00
Ryan Houdek 9b0bb29d78 IR: Implement support for sha256h{2,} 
I keep carrying this patch around. Not yet wired up to the instruction
implementation yet, but I don't want to forget about it.
 2025-04-01 17:53:48 -07:00
Alyssa Rosenzweig 1f08f8df0d IR: allow VUShrNI with bitshift=0 
encodes to Xtn, we need this to narrow.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-31 16:03:18 -04:00
Alyssa Rosenzweig 0038a0b19c IR: plumb Vector_FToISized op 
this exposes the frint* opcodes in a new ir op

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-31 16:03:18 -04:00
Ryan Houdek feab0bce4b x87StackOptimizationPass: Initialize a couple of arrays 
Just to silence some warnings that think these aren't zero initialized
before using.
 2025-03-29 14:02:46 -07:00
Lioncache bfba74dab9 IR: Replace use of deprecated std::is_trivial_v template 
This is deprecated in C++26
 2025-03-29 00:33:39 -04:00
Ryan Houdek bd1d6820b7 Merge pull request #4438 from Sonicadvance1/static_analysis_wars 
Static analysis warning fixes
 2025-03-27 20:30:37 -07:00
Ryan Houdek fbe3a86c4e Merge pull request #4443 from alyssarosenzweig/ra/cleanup 
RA: small cleanups
 2025-03-27 19:46:14 -07:00
Alyssa Rosenzweig 9f399f3313 RegisterAllocationPass: rm unused arg to DecodeSRAReg 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-27 16:45:31 -04:00
Alyssa Rosenzweig 3939213336 RegisterAllocationPass: rm useless assertion 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-27 16:45:31 -04:00
Paulo Matos 4565f2b689 Initialize class fields to null/zero 
Silence a couple of static analyzer warnings.
 2025-03-27 15:35:40 +01:00
Ryan Houdek 4ab6c2252d IR: More validation for shifts 2025-03-27 04:36:41 -07:00
Ryan Houdek 4ebc307744 IR: Ensure BFE ops can't try to extract element larger than size 2025-03-27 04:26:40 -07:00
Ryan Houdek 0b519b29d9 IR/IRDumper: static analysis warnings 2025-03-27 04:26:40 -07:00
Ryan Houdek 8881e8d96e IR/IREmitter: static analysis warnings 2025-03-27 04:26:40 -07:00
Ryan Houdek 9a99608f68 Passes/ConstProp: static analysis warnings 2025-03-27 04:26:40 -07:00
Alyssa Rosenzweig 694e674fe6 IR: tie VExtr 
needed for sve-256 move reduction.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-25 15:22:55 -04:00
Alyssa Rosenzweig 7ebc0f32b8 IR: tie VInsGPR 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-25 15:16:25 -04:00
Alyssa Rosenzweig 68cacc2fc3 IR: tie VFMin/VFMax 
this was missed.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-25 15:16:25 -04:00
Alyssa Rosenzweig 43eb597044 IR: tie VBSL source 
this was missed before, noticed while experimenting with round robin RA.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-25 14:14:21 -04:00
Paulo Matos b18f148575 Abstract AddressMode into its own header 
Also refactor usage of utility functions into x87 Stack Optimization Pass.
 2025-03-20 11:41:26 +01:00
Paulo Matos e18a661b50 Refactor OP_STORESTACKMEM case in x87 Stack Opt Pass 2025-03-18 18:34:06 +01:00
Ryan Houdek 30798556fc Merge pull request #4415 from alyssarosenzweig/opt/avx-zero 
ConstProp: optimize StoreContext(128-bit zero)
 2025-03-17 14:02:06 -07:00
Alyssa Rosenzweig bc87c3d494 ConstProp: optimize StoreContext(128-bit zero) 
Turn this into stp to save a move in a /ton/ of AVX-128 code. It's pretty
annoying to optimize this at the dispatcher level because of the SRA cache, so
doing it in the ConstProp is a nice compromise solution.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-17 16:49:05 -04:00
Ryan Houdek 929b111648 Merge pull request #4405 from Sonicadvance1/static_analysis_again 
Various: More static analysis warnings cleanup
 2025-03-17 13:08:11 -07:00
Ryan Houdek 9f2f10a65f IR: Add new 128-bit vector move operation 
This allows us to slightly optimize some x87 behaviour.
 2025-03-12 22:21:28 -07:00
Ryan Houdek b0b41d00ee Various: More static analysis warnings cleanup 
NFC
 2025-03-12 17:27:41 -07:00
Ryan Houdek a37d6a3841 JIT: Optimize CAS 
Hey kid, want to see a sick trick?

Finally optimal codegen for 64-bit cmpxchg.
 2025-03-07 14:24:45 -08:00
Ryan Houdek 031afbfb18 Various: Adds missing SPDX file headers 
NFC
 2025-03-07 11:34:31 -08:00
Ryan Houdek 66841ce35c IR: Remove some static analysis warnings 
NFC
 2025-03-05 12:30:27 -08:00
Ryan Houdek 2bf87ff40f Various: Removes warnings about uninitialized variables 
NFC. These wouldn't even occur in practice.
 2025-03-04 19:59:26 -08:00
Paulo Matos b5241e0f60 Improve reciprocal estimate and tests 
3DNow Reciprocal estimations did not have enough accuracy. Tests were enabled
to check for accurate values of reciprocals.

* where needed, reciprocal accuracy was increased.
* 3DNow sqrt reciprocal fixed for negative values.
* New helper VFCopySign IR op added.

Fixes #4319.
 2025-02-27 15:07:14 +01:00
Ryan Houdek de6931b1f5 OpcodeDispatcher: Emulate SHA1RNDS4 with ARM sha extensions 
```diff
     "sha1rnds4 xmm0, xmm1, 10b": {
-      "ExpectedInstructionCount": 55,
+      "ExpectedInstructionCount": 10,
```

So I spent a few hours glaring at this instruction. Then spent a few
more glaring in to the sunset and then found the optimization.
 2025-02-22 04:57:58 -08:00
Ryan Houdek cdf6a16efc JIT: Implement ARM VSha1SU1 IR operation 2025-02-19 11:33:38 -08:00
Ryan Houdek bbcd4c168c JIT: Implement support for VSha256U1 operation 2025-02-18 18:03:31 -08:00
Ryan Houdek 7cd4d53fa9 Fixes some instances of auto usage with unintentional copy 
Just switch the uses over to `const auto&`
 2025-02-12 23:51:57 -08:00
Ryan Houdek 3ef695cf70 JIT: Optimize memory stores with zero 
Minor optimization but I've seen it around.
 2025-02-09 22:50:12 -08:00
Billy Laws 0e11a9b7ac FEXCore: Don't copy IR after compilation 
This wastes a significant amount of time when the copies IR is promptly
thrown away after compilation anyway.
 2025-02-04 16:52:16 +00:00
Billy Laws 68c77d12d4 FEXCore: Don't delete IRListView move constructor 2025-02-04 16:51:59 +00:00
Tony Wasserka ebb7137839 IRDumper: Allow const RA data 2025-01-31 15:20:23 +01:00
Paulo Matos 44c65c35c8 Revert "Enable RA of SVE Predicate Registers" 
This reverts commit fcbf0de05a.

The initial user of this code has been re-implemented in  b148cc6c.
This is not needed any longer so we're removing it.
 2025-01-29 11:56:19 +01:00
Paulo Matos 0bccb1ece5 Ensure predicate cache is reset when control flow leaves block 
Whenever the control float leaves the block, it might clobber the
predicate register so we reset the cache whenever that happens.

Fixes #4264
 2025-01-27 20:12:43 +01:00
Tony Wasserka da58e6a597 Fix warnings about unused variables 2025-01-21 12:07:33 +01:00
Tony Wasserka e54b9237c6 Drop use of assume-asserting logging macros 2025-01-21 12:01:33 +01:00
Paulo Matos 2d53867668 x87 fst/fld optimization for different addrmodes 
Includes tests and instcountci files and tests.
When the x87 optimizations were implement, we missed
optimizing different addressing modes. This commit addresses this issue.

Discussed in #4252.
 2025-01-14 16:20:33 +01:00
Ryan Houdek 8cfc016b3f Merge pull request #4265 from pmatos/RevertPredCache 
Revert pred cache
 2025-01-10 12:25:38 -08:00
Paulo Matos cbda688e29 Revert "Cache predicate register generation from pattern" 
This reverts commit 72a4063651.

Caused #4264
 2025-01-10 12:52:11 +01:00
Paulo Matos 159ed07e68 Print arg type f80Bit 2025-01-10 09:14:49 +01:00
LC a6c67ca749 Merge pull request #4251 from Sonicadvance1/ir_numelements_to_elementsize 
IR: Change convention from number of elements to elementsize
 2025-01-04 18:39:24 -05:00