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Code Issues Packages Projects Releases 67 Wiki Activity
11,870 Commits 11 Branches 71 Tags
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Commit Graph
1937 Commits
Author SHA1 Message Date
Ryan Houdek 7ca757bb6d FEXCore: Move CPUInfo to FEX 
This is only ever used in the frontend now.
 2025-04-08 22:54:43 -07:00
Ryan Houdek 5767c61a91 FEXCore/Emitter: Stop creating a vector on the heap 
In the Push/Pop CalleeSavedRegisters these vectors were getting created
on the heap, allocating memory and then just iterating them.

Just use a std::array which makes it stop allocating memory and saves
the number of instructions.
 2025-04-08 18:36:47 -07:00
Ryan Houdek ec1c7797f4 OpcodeDispatcher: Implement support for sha256rnds2 using ARM instructions 
The big one.
 2025-04-02 12:51:03 -07:00
Tony Wasserka 0bd924eb7e Merge pull request #4460 from Sonicadvance1/dead_code 
FEXCore/Frontend: Remove logically dead code
 2025-04-02 09:20:41 +02:00
Ryan Houdek 9b0bb29d78 IR: Implement support for sha256h{2,} 
I keep carrying this patch around. Not yet wired up to the instruction
implementation yet, but I don't want to forget about it.
 2025-04-01 17:53:48 -07:00
Ryan Houdek c3e71de1d7 FEXCore/Frontend: Remove logically dead code 
This code can't get hit.
 2025-04-01 16:09:07 -07:00
Ryan Houdek 1b18bfaff5 Merge pull request #4473 from bylaws/win32-f 
Windows: Small fixups
 2025-04-01 10:53:28 -07:00
Ryan Houdek 8aecdc536c Merge pull request #4471 from alyssarosenzweig/opt/cvtss2si 
Optimize float->integer conversions with Feat_FRINTTS
 2025-04-01 08:52:50 -07:00
Billy Laws 8f50106187 Context: Fix incorrect ifdef on ARM64EC 2025-03-31 23:57:58 +01:00
Billy Laws 02d3a319f9 OpTables: Disable thunk opcodes on win32 
They are of no use here, and are quite frequent in never-taken blocks in Denuvo games
so treating them as invalid avoids wasting some time.
 2025-03-31 23:57:58 +01:00
Ryan Houdek cdaf1c5262 Arm64Emitter: Removes warning 2025-03-31 13:51:50 -07:00
Alyssa Rosenzweig c4f7b27459 OpcodeDispatcher: accelerate F->I conversions with FRINTTS 
this should significantly help perf on supported platforms.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-31 16:09:54 -04:00
Alyssa Rosenzweig 1f08f8df0d IR: allow VUShrNI with bitshift=0 
encodes to Xtn, we need this to narrow.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-31 16:03:18 -04:00
Alyssa Rosenzweig 0038a0b19c IR: plumb Vector_FToISized op 
this exposes the frint* opcodes in a new ir op

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-31 16:03:18 -04:00
Ryan Houdek f9b369c550 Telemetry: Removes unnecessary indirection 
Telemetry value address generation was forcing an indirection at all
times which was unnecessary. These values live in the BSS, zero
initialized at process start and is unnecessary.

Instead change the wrapper defines to directly operate on the enum
passed in which saves an indirection on all of these telemetry
operations (except for the ones in the JIT which are required to be PIC
compliant).

This also fixes an annoying warning about
`FEXCORE_TELEMETRY_STATIC_INIT` causing initialization and destruction
order being unspecified, so two wins.
 2025-03-29 15:10:37 -07:00
Ryan Houdek 0599d80b13 FEXCore/Frontend: Changes how VEX operand encoding flags are encoded 
These three options are mutually exclusive with each other and could
potentially result in invalid encodings of the table on accident.

Change over to a 2-bit bitfield to encode if the operand that consumes
the VEX option is none, destination, 1st src, or 2nd src.

This ensures the table can't ever be incorrectly encoded.
 2025-03-29 13:51:02 -07:00
Lioncache 88e6c48db7 X86Tables: Replace deprecated std::is_trivial template 
This is deprecated in C++26, so we can just use a more specific type trait.
 2025-03-29 00:55:15 -04:00
Ryan Houdek 0ca34d11ad Merge pull request #4454 from alyssarosenzweig/silly-nop 
Fix 66 90 decoding to a nop
 2025-03-28 14:50:02 -07:00
Alyssa Rosenzweig 3a2ca41724 OpcodeDispatcher: handle 66 90 as a NOP 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-28 13:03:34 -04:00
Lioncache ff2c2f1e1f Addressing: Remove unnecessary assert in LoadEffectiveAddress() 
ilog2 already has an assert for this.
 2025-03-28 06:08:08 -04:00
Lioncache 54dbb9f248 OpcodeDispatcher: Fix potential for uninitialized value use in RCRSmallerOp() 
If Src isn't a constant, then no value is actually assigned to SrcConst, so this
can result in uninitialized arithmetic being performed
 2025-03-28 04:45:40 -04:00
Ryan Houdek 21233430aa Merge pull request #4446 from lioncash/cond 
OpcodeDispatcher: Remove unnecessary 128-bit check in VPGATHER()
 2025-03-27 20:30:49 -07:00
Ryan Houdek bd1d6820b7 Merge pull request #4438 from Sonicadvance1/static_analysis_wars 
Static analysis warning fixes
 2025-03-27 20:30:37 -07:00
Lioncache 40b1c32008 OpcodeDispatcher: Remove unnecessary 128-bit check in VPGATHER() 
This is already guaranteed to be true, since it's checked in the outer if,
so this can just be a regular else statement.
 2025-03-27 23:08:59 -04:00
Ryan Houdek b5ed804578 Merge pull request #4444 from lioncash/jitcond 
JIT: Simplify SVE 256 operation asserts
 2025-03-27 19:46:23 -07:00
Ryan Houdek ec976f3f75 Merge pull request #4435 from alyssarosenzweig/opt/pall-pf-af 
Pair PF/AF when spilling static regs
 2025-03-27 19:45:29 -07:00
Lioncache 35ee12e7e9 Addressing: Amend binary AND into logical AND in SelectAddressMode() 
Bitwise AND here is a little odd and was likely intended to be a logical AND.
 2025-03-27 17:29:08 -04:00
Lioncache 4497ab8844 JIT: Simplify SVE 256 operation asserts 
We can make these slightly less verbose.
 2025-03-27 16:55:20 -04:00
Alyssa Rosenzweig cb91d585c3 Arm64Emitter: pair pf/af load/store 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-27 11:07:00 -04:00
Alyssa Rosenzweig 42ea711850 CoreState: squish and rearrange pf_raw/af_raw 
to allow next commit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-27 11:04:08 -04:00
Alyssa Rosenzweig 2cfc42bd6a Arm64Emitter: simplify and fix !preserve_all regs 
stop doing weird special cases. just dump all the regs except what aapcs64 says
we don't have to.

this fixes saving x18 across thunks and things. so probably fixes things *cry*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-27 10:07:27 -04:00
Ryan Houdek 003de2b659 JIT: static analysis warnings 2025-03-27 04:36:41 -07:00
Ryan Houdek 8f9d818368 OpcodeDispathcer: static analysis warnings 2025-03-27 04:26:40 -07:00
Alyssa Rosenzweig 7c42c7798c Arm64Emitter: fix a bunch of preserve_all 
* x18 wasn't getting spilled even though it was supposed to be.
* arm64ec preserve_all definitions were all messed up, specialize these to fix.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-26 16:47:39 -04:00
Ryan Houdek ab9123a427 JIT: Fix typo in VSha256U1 2025-03-25 18:19:37 -07:00
Alyssa Rosenzweig f87edbe1cb JIT: eliminate a zext in bfi 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-25 17:36:59 -04:00
Tony Wasserka 7efd827e78 Merge pull request #4378 from bylaws/volmd 
Implement PE volatile metadata support
 2025-03-25 10:23:53 +01:00
Ryan Houdek d48413cbec Merge pull request #4426 from alyssarosenzweig/opt/shld-improvements 
Drop some masking in shld
 2025-03-24 19:24:51 -07:00
Billy Laws 7a5e08c5ab FEXCore: Use TSO range information when emitting IR 2025-03-24 22:01:49 +00:00
Billy Laws 642903a7bf FEXCore: Support tracking TSO range information 2025-03-24 22:01:49 +00:00
Alyssa Rosenzweig b86cbda03d OpcodeDispatcher: drop useless mask in trivial cmpxchg 
hit by upcoming opt pass, but we don't want to depend on that pass for that.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-24 16:17:04 -04:00
Alyssa Rosenzweig e26b9b12fa OpcodeDispatcher: drop useless zext in shld 
this gets deleted by an upcoming opt pass, but we shouldn't be depending on
the opt pass for it!

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-24 16:00:24 -04:00
Ryan Houdek 9a92f6f743 FEXCore: Remove CPUID option for SHA 
Instead use the HostFeatures option that exists which is controlled by
the {enable,disable}crypto option.
 2025-03-21 19:43:38 -07:00
Ryan Houdek ab7f6484cf Merge pull request #4414 from pmatos/AddrMode-DeusEx 
Fix address modes calculation on 32bit guests
 2025-03-20 13:21:53 -07:00
Paulo Matos b18f148575 Abstract AddressMode into its own header 
Also refactor usage of utility functions into x87 Stack Optimization Pass.
 2025-03-20 11:41:26 +01:00
Alyssa Rosenzweig 61d2a09827 OpcodeDispatcher: fix BT flags 
ZF needs to be preserved.

the new code is the same instr count on flagm although probably an extra uop.
the inst count regression is on flagm, but we can't tolerate broken behaviour.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-18 15:26:47 -04:00
Paulo Matos e18a661b50 Refactor OP_STORESTACKMEM case in x87 Stack Opt Pass 2025-03-18 18:34:06 +01:00
Paulo Matos 16e5777816 Do not attempt direct encoding of 32bit addressing modes 
Fixes #4393
 2025-03-18 15:54:54 +01:00
Paulo Matos 64020e8828 Simplify by merging FSTF64 with FST 2025-03-18 15:54:54 +01:00
Ryan Houdek 929b111648 Merge pull request #4405 from Sonicadvance1/static_analysis_again 
Various: More static analysis warnings cleanup
 2025-03-17 13:08:11 -07:00