Fixes REP CMPS. It needs to also break when ZF == 0
Fixes REPNE SCAS. It shouldn't set ZF to 0 on entry. Could result in erroneous flag setting.
Implements a few new x86 ops
These are whole vector shift instructions and they shift by bytes rather
than bits.
You only get an immediate offset for the instruction.
Implements two new IR ops to account for these instructions
This also doesn't match AArch64 behaviour 100%, requires two
instructions to emulate rather than the single one on the x86-side
If the tmp space grew too large and had to resize then we would have
stale pointers.
Keep around the offset instead so we don't store invalid pointers.
I had to change how blocks are represented to make it easier to parse
This required a fairly substantial refactor that makes it so blocks are
represented differently and we can walk them sequentially.
This will make future analysis easier to deal with.
Had to rewrite the passes and core's parsing of the IR afterwards.
Moved RA in to a optimization pass to be shared between the JIT backends
This works because x86-64 and AArch64 RA can be identical.
Still doesn't support PHI nodes or spilling correctly, this is the first
step in the process of getting there.
Ryan Houdek