LC
edd044752d
[SVE256] Handle SSE insertions for PMADDWD
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See #3799
2026-06-17 22:15:51 -04:00
Ryan Houdek
3a23bb4b73
Merge pull request #5569 from lioncash/cmp
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[SVE256] Handle SSE insertions for CMPSD/CMPSS
2026-06-17 21:32:24 -07:00
LC
99baa4f3d9
[SVE256] Handle SSE insertions for CMPSD/CMPSS
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See #3799
2026-06-17 21:05:31 -04:00
LC
f64d4c571b
[SVE256] Handle SSE insertions for MOVSHDUP/MOVSLDUP
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See #3799
2026-06-17 20:38:58 -04:00
LC
9372fa169a
[SVE256] Handle SSE insertions for MOVSD/MOVSS
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See #3799
2026-06-17 20:09:17 -04:00
LC
daaa6ec129
[SVE256] Handle SSE insertions for aligned and unaligned moves
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See #3799
2026-06-17 19:39:06 -04:00
LC
88afc22d5b
[SVE256] Handle SSE insertions for MOVNTDQA
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See #3799
2026-06-17 19:38:57 -04:00
LC
b7ea9e30df
[SVE256] Handle SSE insertions for MOVH(PD, PD, LPS) and MOVL(PD, PS, HPS)
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See #3799
Gets a few of the moves out of the way.
2026-06-17 17:39:13 -04:00
LC
844c3bb197
[SVE256] Handle SSE insertions for XOR special case
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See #3799
Ensures that our special case maintains insertion behavior
2026-06-17 16:33:05 -04:00
LC
208c6d3eac
[SVE256] Handle SSE insertions for vector unary ops
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See #3799
2026-06-17 14:43:56 -04:00
LC
886a2e74ac
[SVE256] Handle SSE insertions for pack ops
2026-06-17 13:36:18 -04:00
LC
db1d90ec9d
[SVE256] Handle SSE insertions for shuffles
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See #3799
2026-06-17 08:44:45 -04:00
LC
124ce8420a
[SVE256] Handle SSE insertions for PINSR(B,D,Q,W)
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See #3799
2026-06-17 08:22:26 -04:00
LC
4433eaf242
[SVE256] Handle SSE insertions for INSERTPS
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See #3799
2026-06-17 08:11:49 -04:00
LC
5ba070f600
[SVE256] Handle SSE insertions for PSIGN(B,D,W)
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See #3799
2026-06-17 07:59:33 -04:00
LC
2d1a42aa00
[SVE256] Handle SSE insertions for shifts
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See #3799
2026-06-17 06:06:08 -04:00
LC
74d9f5a3e2
[SVE256] Handle SSE insertions for MOVDDUP
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See #3799
2026-06-17 05:13:08 -04:00
LC
634fbb5a73
[SVE256] Handle SSE insertions for Float->Int/Int->Float conversions
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See #3799
2026-06-17 04:44:39 -04:00
LC
e16948bf80
[SVE256] Handle SSE insertions for CVTPD2PS/CVTPS2PD
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See #3799
2026-06-17 03:51:36 -04:00
LC
76c9833ee5
[SVE256] Handle SSE insertions for CMPPD/CMPPS
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See #3799
2026-06-17 03:33:26 -04:00
Ryan Houdek
99662b70ff
Merge pull request #5560 from lioncash/psad
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[SVE256] Handle SSE insertions for more misc ops
2026-06-17 00:14:30 -07:00
LC
fcde9eabbf
[SVE256] Handle SSE insertions for PALIGNR
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See #3799
2026-06-17 02:13:37 -04:00
LC
4ef15951a8
[SVE256] Handle SSE insertions for PACKSS/PACKUS ops
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See #3799
2026-06-17 02:08:24 -04:00
LC
1bc51c2290
[SVE256] Handle SSE insertions for PMULUDQ
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See #3799
2026-06-17 02:00:11 -04:00
LC
be1025901a
[SVE256] Handle SSE insertions for ADDSUBPD/ADDSUBPS
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See #3799
2026-06-17 01:54:55 -04:00
Ryan Houdek
1a606de29f
Merge pull request #5559 from lioncash/phmin
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[SVE256] Handle SSE insertions for PHMINPOSUW, DPPD, and DPPS
2026-06-16 22:50:53 -07:00
LC
454c0b31cb
[SVE256] Handle SSE insertions for MPSADBW
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See #3799
2026-06-17 01:47:21 -04:00
Ryan Houdek
223e0f4e53
Merge pull request #5558 from lioncash/blend
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[SVE256] Handle SSE insertions for blends
2026-06-16 22:34:32 -07:00
LC
3a84091945
[SVE256] Handle SSE insertions for DPPD/DPPS
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See #3799
2026-06-17 01:32:36 -04:00
LC
a0e8f1097f
[SVE256] Handle SSE insertions for PHMINPOSUW
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See #3799
2026-06-17 01:21:19 -04:00
LC
0258fcb116
[SVE256] Handle SSE insertions for blends
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See #3799
2026-06-17 01:05:46 -04:00
LC
3272aa3f08
[SVE256] Handle SSE insertions for ROUNDPD/ROUNDPS
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See #3799
2026-06-17 00:42:20 -04:00
LC
32b11603d8
[SVE256] Handle SSE insertions for PMOVSX/PMOVZX ops
2026-06-17 00:04:03 -04:00
LC
538fd2672d
[SVE256] Handle SSE insertions for PSADBW
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See #3799
2026-06-17 00:04:03 -04:00
LC
3e37724e3e
[SVE256] Handle SSE insertions for PHADDSW
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See #379
2026-06-17 00:04:03 -04:00
LC
1b249ba76b
[SVE256] Handle SSE insertion for PHSUBD/PHSUBW/PHSUBSW
2026-06-17 00:04:03 -04:00
LC
df1295fbd0
[SVE256] Handle SSE insertions for HSUBPD/HSUBPS
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See #3799
2026-06-17 00:04:03 -04:00
LC
dcd71fe126
[SVE256] Handle SSE insertions for PMULHW/PMULHRSW
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See #3799
2026-06-17 00:04:00 -04:00
LC
610ee5db76
[SVE256] Handle SSE insertions for PMADDUBSW
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See #3799
2026-06-16 23:02:25 -04:00
Ryan Houdek
9d5494d9f0
Merge pull request #5555 from lioncash/alu
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[SVE256] Vector: Handle SSE insertion properly for various ALU operations
2026-06-16 19:56:38 -07:00
Ryan Houdek
dd44bc8d00
Merge pull request #5554 from lioncash/vmov
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OpcodeDispatcher: Eliminate redundant moves in VMOVHPOp
2026-06-16 19:47:01 -07:00
Ryan Houdek
110c7cb62b
Merge pull request #5553 from lioncash/bind
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OpcodeDispatcher: Make use of Bind consistently
2026-06-16 19:44:44 -07:00
LC
1d8b6df630
[SVE256] Vector: Handle SSE insertion properly for various ALU operations
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See #3799 for the bulk of the issue explanation. Ensures that emulated
SSE operation on aarch64 don't end up obliterating the upper 128-bit
lane when SVE-256 is present (Adv. SIMD operations zero-extend)
Knocks out quite a few SSE instructions right off the jump.
2026-06-16 22:26:28 -04:00
LC
195058752e
OpcodeDispatcher: Eliminate redundant moves in VMOVHPOp
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Will make removing the TODO in LoadSource regarding partial loads a
little easier.
2026-06-16 17:47:01 -04:00
LC
c62805e86d
OpcodeDispatcher: Make use of Bind consistently
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We had a few places that were using Bind, and a few other places
that were using specializations as a means to composing the instruction
tables. Instead, we can just use Bind consistently, which lets us tidy
up a bunch of the implementations (and gets rid of some unnecessary
codegen).
2026-06-16 15:07:59 -04:00
LC
d15b175c33
OpcodeDispatcher: Move a few stray literal accesses to Literal()
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Same core behavior, but ensures that the immediates are valid literals
when assertions are enabled.
2026-06-16 11:50:48 -04:00
Ryan Houdek
ac12dd55c3
Frontend: Fix vsyscall page tracking.
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Now that NX is tracked in the frontend, we need to ensure that adjusted
RIP pages are tracked correctly. Keep around both instruction stream
pointers, validate the the original RIP is executable, and read from the
adjusted RIP as appropriate.
Fixes #5544
2026-06-03 18:03:31 -07:00
LC
d848cbbc0f
Merge pull request #5543 from Sonicadvance1/165
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FEXCore: Ensure LOCK prefix instructions are handled correctly
2026-06-02 23:39:02 -04:00
Ryan Houdek
8bfae631b1
Frontend: Support raising unimplemented instruction on LOCK failure
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When the LOCK prefix is on an instruction that doesn't support LOCK then
it raises a SIGILL. Make sure to pass that up.
Additionally if the instruction does support lock prefix, has a lock
prefix, but the destination is not memory then that is also invalid.
2026-06-02 19:41:03 -07:00
Ryan Houdek
d00c7cf3a3
Frontend: Support passing the decode failure type through decoding
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Only used for invalid inst currently
2026-06-02 19:41:03 -07:00
LC