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Code Issues Packages Projects Releases 67 Wiki Activity
7,427 Commits 11 Branches 71 Tags
e10afefb2b08d19fe6229a92ecb1e49d52fdc556
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175 Commits
Author SHA1 Message Date
Ryan Houdek 9ba46f429e X8764: Ensure frndint uses host rounding mode 
This previously used `Round_Nearest` which had a bug on Arm64 that it
actually was always using `Round_Host` aka frinti.
Ever since 393cea2e8ba47a15a3ce31d07a6088a2ff91653c[1] this has been fixed
so that `Round_Nearest` actually uses frintn for neaest.

This instruction actually wants to use the host rounding mode.
Once issue with this is that x87 and SSE have different rounding mode
flags and currently we conflate the two in our JIT. This will need to be
fixed in the future.

In the meantime this restores behaviour that it actually uses the host
rounding mode, which fixes black screen and broken vertices in Grim
Fandango Remastered.

[1] e89321dc60 for scalar.
 2023-08-25 16:04:01 -07:00
Ryan Houdek a76c2c57b0 OpcodeDispatcher: Optimize PSHUF{LW, HW, D}! 
This is way more optimal!
 2023-08-25 12:59:40 -07:00
Ryan Houdek 7f63d87295 IR: Adds support for new LoadNamedVectorIndexedConstant IR 2023-08-25 12:59:40 -07:00
Mai bf12f08218 Merge pull request #3002 from Sonicadvance1/optimize_movmaskpd 
OpcodeDispatcher: Optimize 128-bit movmaskpd
 2023-08-25 08:50:28 -04:00
Mai 1f7d138d2a Merge pull request #3008 from Sonicadvance1/optimize_movddup 
OpcodeDispatcher: Optimize movddup from register
 2023-08-25 08:48:40 -04:00
Mai f36f07055a Merge pull request #3007 from Sonicadvance1/optimize_cvtdq2pd 
OpcodeDispatcher: Optimize cvtdq2pd from register source
 2023-08-25 08:47:47 -04:00
Mai 30a1a382c4 Merge pull request #3006 from Sonicadvance1/optimize_movq 
OpcodeDispatcher: Optimizes movq
 2023-08-25 08:46:02 -04:00
Mai 631655dd81 Merge pull request #3005 from Sonicadvance1/nontemporalmoves 
OpcodeDispatcher: Optimize nontemporal moves
 2023-08-25 08:44:48 -04:00
Ryan Houdek 2fbcf2e4a9 OpcodeDispatcher: Optimize movddup from register 
This is now optimal
 2023-08-25 03:44:10 -07:00
Ryan Houdek 00124205e5 OpcodeDispatcher: Optimize cvtdq2pd from register source 
This is now optimal
 2023-08-25 03:39:24 -07:00
Ryan Houdek 81281e2115 OpcodeDispatcher: Optimizes movq 
Removes a redundant move between registers and makes it optimal.
Also removes a couple redundant moves on the avx version.
 2023-08-25 03:29:58 -07:00
Ryan Houdek 1cb2b084b3 OpcodeDispatcher: Generate more optimal code for scalar GPR converts 
1) In the case that we are converted a GPR, don't zero extend it first.
2) In the case that the scalar comes from memory, load it first in an
   FPR and converted it in-place.

These are now optimal in the case of AFP is unsupported.
 2023-08-25 03:19:11 -07:00
Ryan Houdek 189b0da68f JIT/Int: Add support for scalar conversion as well 2023-08-25 03:19:11 -07:00
Ryan Houdek f3679a99ec OpcodeDispatcher: Optimize nontemporal moves 
These are now optimal.
 2023-08-25 03:13:10 -07:00
Ryan Houdek 62156f2152 ARM64JIT: Adds support for scalar cvt 2023-08-25 02:34:30 -07:00
Ryan Houdek 9a54898429 OpcodeDispatcher: Optimize 128-bit movmaskpd 
I'd consider this optimal now.

Thanks to @dougallj for the optimization idea again!
 2023-08-24 17:27:54 -07:00
Ryan Houdek 80d871fb18 Merge pull request #3001 from Sonicadvance1/optimize_cvtps2pd 
OpcodeDispatcher: Optimize cvtps2pd
 2023-08-24 16:09:12 -07:00
Ryan Houdek 3731e6d88b OpcodeDispatcher: Optimize cvtps2pd 
SSE version is now optimal and AVX version gets rid of a redundant move.
 2023-08-24 15:55:11 -07:00
Ryan Houdek c441b238c7 OpcodeDispatcher: Optimize MMX conversion operation 
These instructions are now optimal
 2023-08-24 15:46:19 -07:00
Ryan Houdek 72ce7ddf2d Arm64: Optimize CVT operations for 64-bit variants 
Using 128-bit converts for 64-bit versions cuts their throughput in half
on Cortex. Ensure we use the 64-bit version when possible.
 2023-08-24 15:45:07 -07:00
Ryan Houdek a1210f892a OpcodeDispatcher: Optimize addsubp{s,d} using fcadd 
This extension was added with seemingly Cortex-A710 and turns this
instruction in to two instructions which is quite good.

Needs #2994 merged first.

Huge thanks to @dougallj for the optimization idea!
 2023-08-24 15:00:41 -07:00
Ryan Houdek ba01eac467 IR: Adds support for ARM's FCMA FCADD instruction 2023-08-24 15:00:41 -07:00
Ryan Houdek c5d147322f HostFeatures: Adds support for FCMA 2023-08-24 15:00:41 -07:00
Ryan Houdek 565b30e15e OpcodeDispatcher: Cache named vector constants in the block 
If the named constant of that size gets used multiple times then just
use the previous value if it was in scope.

Makes addsubp{s,d} and phminposuw more optimal for each that are in a
block.

Needs #2993 merged first.
 2023-08-24 14:46:37 -07:00
Ryan Houdek f300196d90 OpcodeDispatcher: Optimize AddSubP{S,D} 
Use a named constant for loading the sign inversion, then EOR the second
source and just FAdd it all.
In a vacuum it isn't a significant improvement, but as soon as more than
one instruction is in a block it will eventually get optimized with
named constant caching and be a significant win.

Thanks to @rygorous for the idea!
 2023-08-23 20:32:51 -07:00
Lioncache 42ccc18606 x86_64/MemoryOps: Fix mislabeled IR op messages 2023-08-23 22:54:36 -04:00
Mai 66c6f96120 Merge pull request #2990 from Sonicadvance1/optimize_pmulh 
OpcodeDispatcher: Optimize PMULH{U,}W using new IR operations
 2023-08-23 22:06:14 -04:00
Ryan Houdek 77b6d854b9 OpcodeDispatcher: Optimize PMULH{U,}W using new IR operations 
SSE implementations are now optimal.
SVE-128bit operation makes it more optimal.
 2023-08-23 18:38:05 -07:00
Ryan Houdek 05b9651279 IR: Implements new vector multiply returning high bits 
SVE implemented a new instruction that does this explicitly, so we
should support it directly.
 2023-08-23 18:38:05 -07:00
Lioncache 26c81224ac OpcodeDispatcher: Remove redundant moves from AESIMC 
Zero-extension will occur automatically upon storing if necessary.

We can also join the SSE and AVX implementations together.
 2023-08-23 21:34:37 -04:00
Lioncache 8a622a3c1a OpcodeDispatcher: Remove redundant moves from VAESEnc 
Zero-extension will occur automatically upon storing if necessary.
 2023-08-23 21:30:06 -04:00
Lioncache f4848fd1a7 OpcodeDispatcher: Remove redundant moves from VAESEncLast 
Zero-extension will occur automatically upon storing if necessary.
 2023-08-23 21:28:14 -04:00
Lioncache d37ce08ae9 OpcodeDispatcher: Remove redundant move from VAESDec 
Zero-extension will occur automatically upon storing if necessary.
 2023-08-23 21:26:49 -04:00
Lioncache a6f1a9f8e8 OpcodeDispatcher: Remove redundant moves from VAESDecLast 
Zero-extension will occur upon storing if necessary.
 2023-08-23 21:25:15 -04:00
Lioncache 52ab3f6a1e OpcodeDispatcher: Remove redundant moves from VAESKeyGenAssist 
Zero-extension will occur upon storing if necessary.

We can also join the AVX implementation with the SSE one.
 2023-08-23 21:22:00 -04:00
Lioncache 410e99ba09 OpcodeDispatcher: Remove redundant moves from VPCLMULQDQOp 
Zero-extension will occur if necessary upon storing.
 2023-08-23 21:18:39 -04:00
Ryan Houdek 6e4765d48b Merge pull request #2989 from lioncash/ins 
Arm64/ConversionOps: Remove redundant moves in AdvSIMD VInsGPR
 2023-08-23 18:09:15 -07:00
Ryan Houdek 172c8f3ba6 Merge pull request #2988 from lioncash/half 
Arm64/ConversionOps: Add missing half-precision conversions to scalar functions
 2023-08-23 17:56:23 -07:00
Lioncache 203a2b1105 Arm64/ConversionOps: Remove redundant moves in AdvSIMD VInsGPR 
If Dst and DestVector alias one another, then we don't need to
move the vector unnecessarily.
 2023-08-23 20:50:21 -04:00
Ryan Houdek 4297e13fcf Merge pull request #2986 from lioncash/ext 
Arm64/VectorOps: Remove redundant moves in SVE VExtr when possible
 2023-08-23 17:40:50 -07:00
Lioncache 5ad56ad52e Arm64/ConversionOps: Add missing half-precision operations to Float_FromGPR_S 
Provides parity with vector operations.
 2023-08-23 20:36:34 -04:00
Lioncache 24e7baf28f Arm64/ConversionOps: Add missing half-precision conversions to Float_FToF 
Provides parity with the vector conversion operations.
 2023-08-23 20:31:49 -04:00
Lioncache b248ae4c04 Arm64/VectorOps: Remove redundant moves from SVE SQSHL 
We don't need to emit a move if the destination and source alias.
 2023-08-23 20:12:09 -04:00
Lioncache 95bea864cf Arm64/VectorOps: Remove redundant moves from SVE SRSHR 
We don't need to perform a move is the destination aliases
the source vector to be shifted.
 2023-08-23 20:10:51 -04:00
Lioncache 47c4507bb6 Arm64/VectorOps: Remove redundant moves from SVE VSQXTUN2 
We don't need to perform a move if the destination aliases the lower vector.
 2023-08-23 20:10:29 -04:00
Lioncache 5ea0b6db28 Arm64/VectorOps: Remove redundant moves from SVE VSQXTN2 
We don't need to perform a move if the destination aliases the
lower vector.
 2023-08-23 20:02:28 -04:00
Mai ee10153d14 Merge pull request #2984 from Sonicadvance1/optimize_pack 
OpcodeDispatcher: Use new IR ops for pack instructions
 2023-08-23 20:02:16 -04:00
Lioncache d0d94adabe Arm64/VectorOps: Remove redundant moves in SVE VExtr when possible 
We don't need to do any moves here is the destination aliases the
lower bits.
 2023-08-23 19:56:10 -04:00
Ryan Houdek 926b8c2c97 Merge pull request #2985 from lioncash/shift 
Arm64/VectorOps: Remove redundant moves from SVE variable/immediate/vector shifts when possible
 2023-08-23 16:41:39 -07:00
Lioncache 18ebcdc9de Arm64/VectorOps: Remove redundant moves in VUshrNI2 
If the destination and VectorLower alias, then we don't need
to emit a movprfx.
 2023-08-23 18:52:32 -04:00