lioncash
d91f2ed6b0
OpcodeDispatcher: Handle VPUNPCKLBW
2022-12-29 16:36:45 +00:00
lioncash
7b30a241c0
OpcodeDispatcher: Handle VPUNPCKLWD
2022-12-29 16:30:12 +00:00
lioncash
aaf8e3757d
OpcodeDispatcher: Handle VPUNPCKLQDQ
2022-12-29 16:21:56 +00:00
lioncash
d9c49c4ce1
OpcodeDispatcher: Handle VPUNPCKLDQ
2022-12-29 16:19:09 +00:00
lioncash
9d05c8a67b
OpcodeDispatcher: Handle VUNPCKLPD
2022-12-29 15:12:36 +00:00
lioncash
be9578551a
OpcodeDispatcher: Handle VUNPCKLPS
2022-12-29 15:00:13 +00:00
lioncash
75a01ed2b6
OpcodeDispatcher: Handle VCVTTSD2SI
2022-12-29 10:49:03 +00:00
lioncash
3ebe141032
OpcodeDispatcher: Handle VCVTSD2SI
2022-12-29 10:43:10 +00:00
lioncash
31e332bd61
OpcodeDispatcher: Handle VCVTTSS2SI
2022-12-29 10:26:19 +00:00
lioncash
764324d557
OpcodeDispatcher: Handle VCVTSS2SI
2022-12-29 10:16:12 +00:00
lioncash
2a7795fe2c
OpcodeDispatcher: Handle VCVTTPD2DQ
2022-12-28 12:01:53 +00:00
lioncash
b00b41b8fa
OpcodeDispatcher: Handle VCVTPD2DQ
2022-12-28 11:54:28 +00:00
lioncash
39396789b1
Interpreter/ConversionOps: Prevent out of bounds/excessive element handling in Vector_FToF
...
Previously this could access more elements than it needs to.
In the case where we pass in a 128-bit vector and perform a 128-bit
operation, only two doubles should be handled, but in this case will
actually try and handle four double elements.
Consider converting doubles within a vector into floats:
e.g. _Vector_FToF(16, 4, Src, 8)
16 is our OpSize
4 is our DestElementSize
Src is our input vector
8 is the SrcElementSize
(OpSize << 1) / Op->SrcElementSize becomes:
(16 << 1) / 8 ->
32 / 8 ->
4
What we actually want it 2 here, we're indexing 128-bit vectors out of
its bounds (not a problem now, since we assume up to 256-bit in the
interpreter).
Similarly with 256-bit vectors
_Vector_FToF(32, 4, Src, 8)
would become:
64 / 8 -> 8
where we actually want 4, since we only have 4 64-bit elements in a
256-bit vector.
This corrects this in the interpreter by just special-casing the 64-bit
calculation.
2022-12-28 11:53:29 +00:00
lioncash
38a2886a59
OpcodeDispatcher: Handle VCVTTPS2DQ
2022-12-28 07:54:16 +00:00
lioncash
bd8e1a80f6
OpcodeDispatcher: Handle VCVTPS2DQ
2022-12-28 07:45:37 +00:00
lioncash
dfa113dcdb
OpcodeDispatcher: Move Vector_CVT_Float_To_Int to helper function
...
This can be reused for the AVX variant.
2022-12-23 17:33:15 +00:00
Ryan Houdek
0e0f3f9290
LookupCache: Use a PMR map for our Blocklinks with monotonic allocator
...
We generate a /lot/ of block links which causes our shutdown time to
take a while for this map. For short running applications this shutdown
time can take a statistically significant amount of time, and this has
been haunting us for a while.
Using a monotonic buffer resource, we can cut the dellocation time down
to effectively zero on cache clear and shutdown.
For short running applications this basically means we clear their
shutdown time, for long running applications this means a cache clear is
less painful.
I've measured up to 2ms , but more often this takes ~0.5ms before
optimization. Now it is consistently ~0.25ms on a short running
application.
Times will vary /greatly/ depending on how full it has filled this map.
2022-12-23 09:41:54 -08:00
Mai
bf7d0f7ed9
Merge pull request #2287 from Sonicadvance1/rename_getreg
...
Arm64: Rename GetSrcPair, GetDst, and GetSrc
2022-12-22 08:40:10 +00:00
lioncash
94cb2ddae7
OpcodeDispatcher: Handle VPMULHRSW
2022-12-22 08:21:35 +00:00
lioncash
0496f8d5c1
OpcodeDispatcher: Move PMULHRSW impl to helper
2022-12-22 08:13:43 +00:00
Ryan Houdek
37a9588855
Arm64: Rename GetSrcPair to GetRegPair
...
This matches the other handler's names and isn't only for source
registers, but also destination registers.
2022-12-22 00:03:41 -08:00
Ryan Houdek
24f72b5f30
Arm64: Rename GetDst & GetSrc to GetVReg
...
These only resolved to getting vector registers now and having
duplicating handlers for it was just confusing.
2022-12-21 23:59:21 -08:00
lioncash
d927c4a903
OpcodeDispatcher: Handle VPMULHUW
2022-12-22 07:52:27 +00:00
lioncash
12afe95602
OpcodeDispatcher: Handle VPMULHW
2022-12-22 07:52:24 +00:00
lioncash
7e715b9e04
OpcodeDispatcher: Move PMULHW impl to helper
...
This can be used with AVX variants.
2022-12-22 07:33:26 +00:00
lioncash
4f9402e5dd
OpcodeDispatcher: Handle VPHMINPOSUW
2022-12-22 02:46:08 +00:00
lioncash
789093d158
OpcodeDispatcher: Move VPHMINPOSUW impl to separate function
...
This will be used with the AVX variant.
2022-12-22 02:38:31 +00:00
lioncash
d672528e62
OpcodeDispatcher: Handle VPMULUDQ
2022-12-22 02:18:37 +00:00
lioncash
d7c959090d
OpcodeDispatcher: Handle VPMULDQ
2022-12-22 02:08:53 +00:00
lioncash
0a4846a524
OpcodeDispatcher: Factor PMULLOp impl to regular function
...
This can be reused for the AVX implementations.
2022-12-22 01:30:06 +00:00
lioncash
2d9cb65d5c
OpcodeDispatcher: Handle VCMPSD
2022-12-21 20:46:07 +00:00
lioncash
e21002e0d7
OpcodeDispatcher: Handle VCMPSS
2022-12-21 20:39:13 +00:00
Ryan Houdek
ce351282f2
Merge pull request #2282 from lioncash/debug
...
OpcodeDispatcher: Remove lingering debug log from VPFCMPOp
2022-12-21 00:53:13 -08:00
lioncash
ab41856328
OpcodeDispatcher: Remove lingering debug log from VPFCMPOp
2022-12-21 08:40:27 +00:00
Ryan Houdek
345e9b97bf
Merge pull request #2281 from lioncash/assert
...
OpcodeDispatcher: Convert runtime assert to static_assert in SHUFOps
2022-12-21 00:23:24 -08:00
lioncash
f850a02d3f
OpcodeDispatcher: Convert runtime assert to static_assert in SHUFOps
2022-12-21 08:05:32 +00:00
lioncash
983b53a0c2
OpcodeDispatcher: Handle VCMPPD
2022-12-21 06:12:14 +00:00
lioncash
10a6b5794b
OpcodeDispatcher: Handle VCMPPS
2022-12-21 05:57:24 +00:00
lioncash
2c5aceb9b6
OpcodeDispatcher: Factor out VFCMPOp impl into a regular function
...
This can be used with AVX implementations.
2022-12-21 05:27:10 +00:00
Ryan Houdek
1668db046d
Merge pull request #2279 from lioncash/psrldq
...
OpcodeDispatcher: Handle VPSRLDQ
2022-12-20 21:06:57 -08:00
lioncash
825e921940
OpcodeDispatcher: Handle VPSRLDQ
2022-12-21 04:51:49 +00:00
lioncash
c06f0b7cb3
OpcodeDispatcher: Remove usage of VMov in VPSLLDQOp
...
The extract operation essentially does this for us.
2022-12-21 04:13:26 +00:00
Ryan Houdek
4aed60ee3d
Merge pull request #2277 from lioncash/cvt
...
OpcodeDispatcher: Handle VCVTDQ2PD/VCVTDQ2PS
2022-12-20 20:02:12 -08:00
lioncash
da9f7ec31f
OpcodeDispatcher: Handle VCVTDQ2PD
2022-12-21 03:45:00 +00:00
lioncash
8ec932fc4c
OpcodeDispatcher: Handle VCVTDQ2PS
2022-12-21 03:44:56 +00:00
lioncash
6f35a23161
x86_64/ConversionOps: Don't clear upper lane in Vector_SToF
...
If Dst and Vector are the same, this will obliterate the top lane data
that needs to be operated on in the 128-bit case.
2022-12-21 03:40:38 +00:00
lioncash
bd70af9724
OpcodeDispatcher: Move Vector_CVT_Int_To_Float impl to regular function
...
This can be used with the AVX implementation as well.
2022-12-21 02:23:04 +00:00
lioncash
bdba062f72
VEXTables: Amend VCVTTPS2DQ name
2022-12-21 02:17:31 +00:00
lioncash
d591b1ed8c
Interpreter: Prevent overrun with 256-bit VExtr
2022-12-21 01:51:25 +00:00
lioncash
3bae4a225c
OpcodeDispatcher: Handle VPSLLDQ
2022-12-21 01:46:17 +00:00
lioncash