Register class for loadstores must be declared upfront.
This was causing a pain point when we were trying to load <16byte in to
FPRs, which was requiring a GPR<->FPR dance.
I had to change how blocks are represented to make it easier to parse
This required a fairly substantial refactor that makes it so blocks are
represented differently and we can walk them sequentially.
This will make future analysis easier to deal with.
Had to rewrite the passes and core's parsing of the IR afterwards.
Moved RA in to a optimization pass to be shared between the JIT backends
This works because x86-64 and AArch64 RA can be identical.
Still doesn't support PHI nodes or spilling correctly, this is the first
step in the process of getting there.
Ryan Houdek