Ryan Houdek
d5cb87d1eb
Adds Phi helper functions to OpDispatcher
2020-03-06 07:56:08 +02:00
Scott Mansell
26141e426a
Fix unsigned/signed compare conditions
...
Also, rename to match the LLVM naming style, which is less confusing.
2020-03-06 07:56:07 +02:00
Ryan Houdek
fb17e4d440
Adds atomic ops to the Interpreter
2020-03-06 07:56:07 +02:00
Scott Mansell
7f840aa3e9
Basic FADD implementation
...
Only handles addition of two positive numbers
2020-03-06 07:56:07 +02:00
Ryan Houdek
3d0c11c770
Fixes VSLI and VSRI on AArch64
...
I misunderstood these instructions on the AArch64 side.
VSLI/VSRI doesn't operate on 128bit wide vectors. Its scalar version
only works on 64bit.
We have to move the vector to GPRs and do some bit twiddling then move
the full 128bit vector back after the fact
2020-03-06 07:56:07 +02:00
Ryan Houdek
e3bbb8a580
Fixes a couple AArch64 JIT Atomic Fetches
...
Swap wasn't storing in to destinationo
And and Sub weren't using the right registers
2020-03-06 07:56:07 +02:00
Ryan Houdek
520d098e23
Implements VCastFromGPR in AArch64 JIT
2020-03-06 07:56:07 +02:00
Scott Mansell
f5bf8eaeb2
Add FST/FSTP m80
2020-03-06 07:56:07 +02:00
Scott Mansell
bbd951603f
Add FLD m32/m64
...
Currently produces incorrect results on infinities/denormals.
2020-03-06 07:56:06 +02:00
Scott Mansell
1dee7cb037
Append x87 flags to cpustate flags[]
2020-03-06 07:56:06 +02:00
Scott Mansell
4fe10ca130
Add Load/StoreContextIndexted IR instructions
...
Useful for things like x87 where instructions can dynamically index
into a resgister file.
This commit includes support for irint and x86 jit.
2020-03-06 07:56:06 +02:00
Scott Mansell
bb879a7beb
Fix FLD instruction flags
2020-03-06 07:56:06 +02:00
Scott Mansell
4051d529df
Fix size of movesd xmm <-- m64
2020-03-06 07:56:06 +02:00
Ryan Houdek
8cd865a91e
Removes debug log
2020-03-06 07:56:06 +02:00
Ryan Houdek
f4a5770f1e
Implements lock prefix on some commonly used ops
2020-03-06 07:56:06 +02:00
Ryan Houdek
3a608efbc7
Adds new atomic ops to the x86 JIT
2020-03-06 07:56:06 +02:00
Ryan Houdek
9d8b60af5c
Work on x86 JIT ASM dispatcher
2020-03-06 07:56:05 +02:00
Ryan Houdek
96b0214bc1
Add new atomic ops to the AArch64 JIT
2020-03-06 07:56:05 +02:00
Ryan Houdek
e1d2a934e2
Fixes the scalar SSE ops and MOVD
2020-03-06 07:56:05 +02:00
Ryan Houdek
6fb2d1aa1f
Implements XADD x86 instruction
2020-03-06 07:56:05 +02:00
Ryan Houdek
931df90a4e
Fixes FINDMSB IR op in the x86 JIT
2020-03-06 07:56:05 +02:00
Ryan Houdek
1b58aa61f7
Implements new atomic ops in the x86 JIT
2020-03-06 07:56:05 +02:00
Ryan Houdek
6544570264
Implements VUSHR IR op in x86 JIT
2020-03-06 07:56:04 +02:00
Ryan Houdek
a684bc1aff
Implements SplatVector2/4 in x86 JIT
2020-03-06 07:56:04 +02:00
Ryan Houdek
2858adc0d3
Fixes MOVSD x86 instruction
2020-03-06 07:56:04 +02:00
Ryan Houdek
28142703ee
Fixes BTR/BTS op when destination is GPR
2020-03-06 07:56:04 +02:00
Ryan Houdek
77e7a453d3
Adds BTC x86 instruction
2020-03-06 07:56:04 +02:00
Scott Mansell
0d782bd515
Fix handling of 8/16bit loads in x64 jit.
...
Need to sign extend, otherwise junk from upper bits
can mess things up.
2020-03-06 07:56:03 +02:00
Scott Mansell
5429721350
Also make MOVXS accept the 66 prefix
2020-03-06 07:56:03 +02:00
Scott Mansell
7ec68ce815
Fix decoding legacy 66 0F XX insturctions.
2020-03-06 07:56:03 +02:00
Ryan Houdek
e2b30d9c02
Adds REV IR op to x86 JIT and AArch64 JIT
2020-03-06 07:56:03 +02:00
Ryan Houdek
255138dcc4
Adds a bunch of new instructions to the OpcodeDispatcher
2020-03-06 07:56:03 +02:00
Ryan Houdek
962669cd17
Adds new IR ops to the LLVM JIT
2020-03-06 07:56:03 +02:00
Ryan Houdek
29b7ddb67f
Adds new IR ops to the x86-64 JIT
2020-03-06 07:56:03 +02:00
Ryan Houdek
fc0ce3d1dc
Adds new IR ops to the AArch64 JIT
2020-03-06 07:56:02 +02:00
Ryan Houdek
e9d1ec6aff
Adds new IR ops to the interpreter
2020-03-06 07:56:02 +02:00
Ryan Houdek
6b636c3c26
Fixes a couple of instructions in the x86Tables
2020-03-06 07:56:02 +02:00
Ryan Houdek
2f5e2ea066
Fixes LODS and SCAS x86Table flags
2020-03-06 07:56:02 +02:00
Ryan Houdek
3bb9197e6a
Adds VAND IR Op
2020-03-06 07:56:02 +02:00
Ryan Houdek
a858296ecd
Removes SSE41, SSE42, and AVX support from CPUID
2020-03-06 07:56:01 +02:00
Scott Mansell
2babc1292c
GdbServer: Breakpoint intergation
2020-03-06 07:56:01 +02:00
Scott Mansell
9a89741ff2
gdbServer: Allow continuing
2020-03-06 07:56:01 +02:00
Scott Mansell
e050eace1d
Refactor context start/pause/step interface
2020-03-06 07:56:01 +02:00
Scott Mansell
545b542f9b
GdbServer: Implement xml target for register order
...
We can now simply memcpy much of memory state.
2020-03-06 07:56:01 +02:00
Scott Mansell
e44b3ca495
Gdbserver: Implement enough to reach gdb prompt
...
Memory is implemented, but without any checking or
invalidation.
Registers just hardcode a RIP for my test elf.
But GDB can read the elf over tcp, initilize and allow you to create breakpoints, which get
writen back before continue (which is not hooked up)
2020-03-06 07:56:01 +02:00
Scott Mansell
17ffe5a7b2
GdbServer: Support a few more packets
2020-03-06 07:56:01 +02:00
Scott Mansell
23db0f66ec
Add a skeleton of a GdbServer
2020-03-06 07:56:01 +02:00
Ryan Houdek
e0e708a9c0
Fixes three instructions necessary for shared apps to run
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Fixes MOVHPD which was failing.
Fixes FXSTOR and FXSAVE which was accidently loading the memory location
rather than doing an LEA of the address.
2020-03-06 07:56:01 +02:00
Ryan Houdek
e9be5430b9
Adds a couple new IR ops for easy movement of registers between classes.
2020-03-06 07:56:01 +02:00
Ryan Houdek
af5a562508
Fixes bug in STOS and CMPS
...
We were storing one too many elements. So even if the counter register
was zero it would do a store or comparison
2020-03-06 07:56:00 +02:00
Ryan Houdek