Ryan Houdek
d2bfb39b54
Disable RDRand in CPUID
2020-03-06 07:56:15 +02:00
Ryan Houdek
7ade645af2
Adds vector compare ops to OpDispatcher
2020-03-06 07:56:14 +02:00
Ryan Houdek
39802cc464
Adds a couple nop implementation of ops in OpDispatcher
2020-03-06 07:56:14 +02:00
Ryan Houdek
67ac4f015f
Adds ANDN to OpDispatcher
2020-03-06 07:56:14 +02:00
Ryan Houdek
1f4418b463
Adds missing move to OpDispatcher
2020-03-06 07:56:14 +02:00
Ryan Houdek
134fa50f8b
Adds fsqrt and frsqrt to OpDispatcher
2020-03-06 07:56:14 +02:00
Ryan Houdek
e260378736
Fix a couple x86 instruction definitions
2020-03-06 07:56:14 +02:00
Ryan Houdek
dacd20f44b
Fixes interpreter temp allocation size
2020-03-06 07:56:14 +02:00
Ryan Houdek
9bc899aba0
Changes CMPS to not break RA
...
RA isn't happy with how this is arranged, so it needs to be changed
until RA is good enough to support it
2020-03-06 07:56:14 +02:00
Ryan Houdek
c39f23802c
Fixes ULE Select on x86 JIT
2020-03-06 07:56:14 +02:00
Ryan Houdek
9b19d23977
Fixes FindMSB in Interpreter and Arm64 JIT
2020-03-06 07:56:14 +02:00
Ryan Houdek
2889c860d4
Adds new vector IR ops
2020-03-06 07:56:14 +02:00
Ryan Houdek
a8d7549b13
Fixes CPUID call in Arm64 JIT
2020-03-06 07:56:13 +02:00
Ryan Houdek
69d6c09436
Fixes AArch64 JIT compiling
2020-03-06 07:56:13 +02:00
Ryan Houdek
07faaaa0fd
Make sure to not do pops at function end if from within custom dispatch for x86
2020-03-06 07:56:13 +02:00
Ryan Houdek
92e4be828f
Implements new RA pass that supports PHI nodes
...
Has a heuristic that changes from a map lookup and a linear scan
depending on the number of SSA values. Map lookup is faster for larger
blocks while for smaller blocks linear scan is faster.
Block scan is 1.5x - 2x faster for a 30k SSA value block I was looking
at.
2020-03-06 07:56:13 +02:00
Ryan Houdek
d5cb87d1eb
Adds Phi helper functions to OpDispatcher
2020-03-06 07:56:08 +02:00
Scott Mansell
26141e426a
Fix unsigned/signed compare conditions
...
Also, rename to match the LLVM naming style, which is less confusing.
2020-03-06 07:56:07 +02:00
Ryan Houdek
fb17e4d440
Adds atomic ops to the Interpreter
2020-03-06 07:56:07 +02:00
Scott Mansell
7f840aa3e9
Basic FADD implementation
...
Only handles addition of two positive numbers
2020-03-06 07:56:07 +02:00
Ryan Houdek
3d0c11c770
Fixes VSLI and VSRI on AArch64
...
I misunderstood these instructions on the AArch64 side.
VSLI/VSRI doesn't operate on 128bit wide vectors. Its scalar version
only works on 64bit.
We have to move the vector to GPRs and do some bit twiddling then move
the full 128bit vector back after the fact
2020-03-06 07:56:07 +02:00
Ryan Houdek
e3bbb8a580
Fixes a couple AArch64 JIT Atomic Fetches
...
Swap wasn't storing in to destinationo
And and Sub weren't using the right registers
2020-03-06 07:56:07 +02:00
Ryan Houdek
520d098e23
Implements VCastFromGPR in AArch64 JIT
2020-03-06 07:56:07 +02:00
Scott Mansell
f5bf8eaeb2
Add FST/FSTP m80
2020-03-06 07:56:07 +02:00
Scott Mansell
bbd951603f
Add FLD m32/m64
...
Currently produces incorrect results on infinities/denormals.
2020-03-06 07:56:06 +02:00
Scott Mansell
1dee7cb037
Append x87 flags to cpustate flags[]
2020-03-06 07:56:06 +02:00
Scott Mansell
4fe10ca130
Add Load/StoreContextIndexted IR instructions
...
Useful for things like x87 where instructions can dynamically index
into a resgister file.
This commit includes support for irint and x86 jit.
2020-03-06 07:56:06 +02:00
Scott Mansell
bb879a7beb
Fix FLD instruction flags
2020-03-06 07:56:06 +02:00
Scott Mansell
4051d529df
Fix size of movesd xmm <-- m64
2020-03-06 07:56:06 +02:00
Ryan Houdek
8cd865a91e
Removes debug log
2020-03-06 07:56:06 +02:00
Ryan Houdek
f4a5770f1e
Implements lock prefix on some commonly used ops
2020-03-06 07:56:06 +02:00
Ryan Houdek
3a608efbc7
Adds new atomic ops to the x86 JIT
2020-03-06 07:56:06 +02:00
Ryan Houdek
9d8b60af5c
Work on x86 JIT ASM dispatcher
2020-03-06 07:56:05 +02:00
Ryan Houdek
96b0214bc1
Add new atomic ops to the AArch64 JIT
2020-03-06 07:56:05 +02:00
Ryan Houdek
e1d2a934e2
Fixes the scalar SSE ops and MOVD
2020-03-06 07:56:05 +02:00
Ryan Houdek
6fb2d1aa1f
Implements XADD x86 instruction
2020-03-06 07:56:05 +02:00
Ryan Houdek
931df90a4e
Fixes FINDMSB IR op in the x86 JIT
2020-03-06 07:56:05 +02:00
Ryan Houdek
1b58aa61f7
Implements new atomic ops in the x86 JIT
2020-03-06 07:56:05 +02:00
Ryan Houdek
6544570264
Implements VUSHR IR op in x86 JIT
2020-03-06 07:56:04 +02:00
Ryan Houdek
a684bc1aff
Implements SplatVector2/4 in x86 JIT
2020-03-06 07:56:04 +02:00
Ryan Houdek
2858adc0d3
Fixes MOVSD x86 instruction
2020-03-06 07:56:04 +02:00
Ryan Houdek
28142703ee
Fixes BTR/BTS op when destination is GPR
2020-03-06 07:56:04 +02:00
Ryan Houdek
77e7a453d3
Adds BTC x86 instruction
2020-03-06 07:56:04 +02:00
Scott Mansell
0d782bd515
Fix handling of 8/16bit loads in x64 jit.
...
Need to sign extend, otherwise junk from upper bits
can mess things up.
2020-03-06 07:56:03 +02:00
Scott Mansell
5429721350
Also make MOVXS accept the 66 prefix
2020-03-06 07:56:03 +02:00
Scott Mansell
7ec68ce815
Fix decoding legacy 66 0F XX insturctions.
2020-03-06 07:56:03 +02:00
Ryan Houdek
e2b30d9c02
Adds REV IR op to x86 JIT and AArch64 JIT
2020-03-06 07:56:03 +02:00
Ryan Houdek
255138dcc4
Adds a bunch of new instructions to the OpcodeDispatcher
2020-03-06 07:56:03 +02:00
Ryan Houdek
962669cd17
Adds new IR ops to the LLVM JIT
2020-03-06 07:56:03 +02:00
Ryan Houdek
29b7ddb67f
Adds new IR ops to the x86-64 JIT
2020-03-06 07:56:03 +02:00
Ryan Houdek