Ryan Houdek
d1161de4e4
Removes warning from Static Register Allocation Pass
2021-01-31 08:00:58 -08:00
Stefanos Kornilios Mitsis Poiitidis
1f7d815f3a
LookupCache: Fix crash on L2 insertion
2021-01-29 22:00:07 +02:00
Stefanos Kornilios Mitsis Poiitidis
9ecde7a0b8
Interpreter: Move execution to IntepreterOps::ExecuteIR, single core refactor
2021-01-29 15:17:37 +02:00
Stefanos Kornilios Mitsis Poiitidis
972219043d
Core: Refactor compilation driver, lifetime of objects
2021-01-29 10:42:55 +02:00
Stefanos Kornilios Mitsis Poiitidis
0e00d3dc15
RA: Optimize RAData
2021-01-29 10:42:48 +02:00
Stefanos Kornilios Mitsis Poiitidis
a45c2c34e9
RA: Use RAData directly
2021-01-29 10:42:40 +02:00
Stefanos Kornilios Mitsis Poiitidis
513112919b
RA: Move allocation data to RAData
2021-01-29 10:42:40 +02:00
Stefanos Kornilios Mitsis Poiitidis
791aa4c32c
LookupCache: Add a third level cache that will always resolve all known blocks
2021-01-29 01:53:12 +02:00
Stefanos Kornilios Mitsis Poiitidis
0c9e05ed8f
Rename BlockCache to LookupCache
2021-01-29 01:31:48 +02:00
Ryan Houdek
2d8b70bbd5
Merge pull request #710 from Sonicadvance1/brk_improvements
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More improvements to BRK handling
2021-01-27 10:49:07 -08:00
Stefanos Kornilios Mitsis Poiitidis
f872e178ac
Merge pull request #718 from Sonicadvance1/32bit_sigret_handler
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Forces SIGRET handler to the lower 32bits VA on 32bit processes
2021-01-27 20:16:51 +02:00
Ryan Houdek
a5d9e62cc6
More improvements to BRK handling
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Base size is now only one page in size. We will then increment that BRK
size by 8MB alignments. 256MB for 32bit applications was causing some
applications on the edge to run out of virtual memory
I was hitting some 32bit applications that were being fairly mean with
BRK. They were allocating all of BRK space then running out of virtual
memory space with its mmap handler fallback after freeing BRK space.
This means we now munmap BRK pages on release for the guest, similar to
behaviour that Linux does.
Additionally I had an application that was getting very upset that BRK
wasn't actually at the end of program space. So allocate at the end of
program space like expected.
brk test now passes from gvisor
2021-01-27 10:12:25 -08:00
Stefanos Kornilios Mitsis Poiitidis
ec31dc0872
Merge pull request #716 from Sonicadvance1/describe_tag
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Puts the FEX describe tag in CPUID
2021-01-27 20:10:46 +02:00
Ryan Houdek
2437b89c7b
Forces SIGRET handler to the lower 32bits VA on 32bit processes
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This is visible to the guest process so for 32bit it needs to be in the
lower 32bits.
2021-01-27 07:54:30 -08:00
Ryan Houdek
5673a0e213
Puts the FEX describe tag in CPUID
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This is what shows up in /proc/cpuinfo
example on tagged release: 'model name : FEX-2101'
example on untagged release: 'model name : FEX-2101-64-g536be23f'
Fixes #661
2021-01-27 07:20:14 -08:00
Ryan Houdek
3df344a78d
Fixes some asserts from vixl and a bug in ExitSpillSRA
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Assembler by default doesn't allow you to use the assembler. Needs a
CodeBufferCheckScope.
Labels with binds and not links will throw an assert.
ExitSpillSRA was using b instead of bind incorrectly.
Thus branching to a invalid location
2021-01-27 00:53:27 -08:00
Ryan Houdek
6bca290611
Implements VBSL on AArch64
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This isn't quite optimal without RA constraints
2021-01-26 03:01:48 -08:00
Ryan Houdek
513cb27825
Add TSX names to decode tables so we know what they are
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Rather than just stating UND
We can't support this until we have an ARM CPU that supports TME and
more robust multiblock.
2021-01-26 02:03:42 -08:00
Stefanos Kornilios Mitsis Poiitidis
b0365871b6
OpDisp: Address most 32-bit rip size issues
2021-01-25 15:04:12 +02:00
Ryan Houdek
d4ffea5c31
Merge pull request #670 from FEX-Emu/skmp/faster-ra
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IR: Optimize runtime of optimization passes
2021-01-22 04:54:08 -08:00
Stefanos Kornilios Mitsis Poiitidis
0546da7a75
Address review feedback
2021-01-22 11:01:36 +02:00
Stefanos Kornilios Mitsis Poiitidis
8b025d4c26
IRLoader: Actually set EntryRIP if the IR was parsed
2021-01-21 22:19:16 +02:00
Stefanos Kornilios Mitsis Poiitidis
3bd8731b26
IR: Add CONFIG_VALIDATE_IR_PARSER, enable it on TestHarnessRunner
2021-01-21 21:38:41 +02:00
Stefanos Kornilios Mitsis Poiitidis
13613c6de1
IR: Change ValidateCode to use two uint64_t instead of __uint128_t
2021-01-21 21:37:58 +02:00
Stefanos Kornilios Mitsis Poiitidis
1177c375ff
IR: Further parser cleanups, add fence types
2021-01-21 21:17:27 +02:00
Stefanos Kornilios Mitsis Poiitidis
072067b5fd
IR: Split parser from IRLoader, add IR::Parse()
2021-01-21 19:17:51 +02:00
Stefanos Kornilios Mitsis Poiitidis
773e5866b4
Merge pull request #666 from Sonicadvance1/handle_unaligned_caspal32
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Handle unaligned cmpxchg and cmpxchg8b on ARMv8.1+
2021-01-21 13:30:18 +02:00
Stefanos Kornilios Mitsis Poiitidis
00ca576644
IRCompaction: Only memset in debug
2021-01-21 13:06:43 +02:00
Stefanos Kornilios Mitsis Poiitidis
036771d825
IR: Fix Printing and Parsing for float conds
2021-01-21 10:16:08 +02:00
Ryan Houdek
633ea045e5
Handles unaligned cmpxchg/cmpxchg8b in SIGBUS handler
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cmpxchg/cmpxchg8b doesn't have alignment requirements on x86, which means
applications rely on unaligned behaviour support with it.
Steam relies on this to work for a linked list array of jobs in some
internal job queueing system. It will end up always aligning by offsets
of 4 since it stores a couple of pointers.
Doesn't currently support the case of unaligned cmpxchg8b crossing a
cacheline, which ends up being semi-broken depending on which x86
behaviour the application is expected.
Intel CPUs do the "Big ring lock" or "split locks". Which means accesses
across cachelines are atomic.
AMD CPUs will tear the value across the cacheline, which is expected x86
behaviour by spec.
If they are expecting Intel behaviour, then that application is just
broken on non-Intel platforms unless they are fine with a tear.
2021-01-20 16:07:50 -08:00
Stefanos Kornilios Mitsis Poiitidis
0e7db64ac7
RA: Run compation after spilling, not before
2021-01-21 01:01:02 +02:00
Stefanos Kornilios Mitsis Poiitidis
ac1036ac92
IR: Sync Invalid class with RA
2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis
9c462eb400
ConsProp: Revert to ordered set for identical codegen
2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis
8aef9cb6a7
RA: Exit after first spill per iteration is found
2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis
d3fc85e18d
RA: Make spans at least 1 offset long
2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis
9f3ce47917
RA: Expire ending intervals before starting new ones
2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis
a9332e604a
JIT/x64: Fix VAddV
2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis
e7e6b6654f
RA: Cleanups
2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis
c3682f9a3b
RA: Fix several bugs, get rid of virtual registers, remove unused complexity
2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis
47ee9af96c
ConstProp: Keep pools in heap
2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis
10b6fb02c4
RA: Rename CalculatePrecessors to CalculatePredecessors
2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis
9c760ff83b
RA: Get OP_JUMP/CONDJUMP without loop in CalculatePrecessors
2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis
f3e19ef015
DSE: No need to loop to find branching op
2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis
6bdf785223
DSE: Optimize map lookups
2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis
997650bafc
DSE: Merge logic more for perf
2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis
56ca73191d
DSE: Merge Flag/GPR/FPR passes for perf
2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis
900fc6d2a7
ConstProp: Switch maps to unordred_maps
2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis
af94e24ba3
RA: Simplify and optimize data structures
2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis
6380ab6bfd
RA: Optimize register conflict handling
2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis
91ddc1dd38
RCLSE: Optimize FindMemberInfo to be O(1)
2021-01-20 04:26:06 +02:00
