5 Commits

Include renames

Author	SHA1	Message	Date
Ryan Houdek	03f63f99a8	FEXCore: Moves StringUtils to FEXCore headers ... Once gdbserver gets moved to the frontend this will need to be in the includes.	2023-11-02 20:09:12 -07:00
Alyssa Rosenzweig	2a2619c0f5	IR: Add bit masking selects ... Add new synthetic condition codes that do an AND as their relational operator, testing the result. This is 1 IR op for things like (A & B) == 0 ? C : D This can translate to tst A, B csel A, B, eq In the future, if A is the NZCV register and B is a supported immediate, eg (NZCV & 0x80000000) == 0 ? C : D this will be able to translate to a single instruction with the appropriate condition csel A, B, pl but that needs RA support. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2023-09-22 19:07:42 -04:00
Ryan Houdek	afda4d6b7a	FEXCore/Interface/IR: Adds SPDX identifier	2023-09-19 17:33:14 -07:00
Ryan Houdek	e4bb0df486	IR: Convert all Move+Atomic+ALU ops from implicit to explicit size ... The number of times the implicit size calculation in GPR operations has bit us is immeasurable and was a mistake from the start of the project. The vector based operations never had this problem since they were explicitly sized for a long time now. This converts the base IR operations to be explicitly sized, but adds implicit sized helpers for the moment while we work on removing implicit usage from the OpcodeDispatcher. Should be NFC at this moment but it is a big enough change that I want it in before the "real" work starts.	2023-08-27 01:35:08 -07:00
Alyssa Rosenzweig	af21b8f3c7	Move External/FEXCore/ to FEXCore/ ... It is not an external component, and it makes paths needlessly long. Ryan seemed amenable to this when we discussed on IRC earlier. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2023-08-17 16:32:16 -04:00