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224 Commits
Author SHA1 Message Date
Ryan Houdek b83cbcb33c ConstProp: Bandage fix for instcountci 
Fixed offset x86 code doesn't quite solve the issue, so adjust this
heuristic just to get instcounci to stop flaking.

This code is going to heavily change soon anyway so +50 doesn't change
much.
 2024-05-18 18:06:25 -07:00
Ryan Houdek 3eb7a5b998 Merge pull request #3632 from pmatos/RemoveBlocks 
Use erase-remove idiom to remove element
 2024-05-16 10:50:50 -07:00
Alyssa Rosenzweig bf3a09e5e3 ConstProp: remove x86 jit leftover 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-05-16 09:21:41 -04:00
Paulo Matos 9ca4868833 Use erase-remove idiom to remove element 
Fixes #3631
 2024-05-16 10:16:01 +02:00
Ryan Houdek d19b57a52e FEXCore: Get rid of DeferredSignalFaultAddress and use the InterruptFaultPage 
Arm64ec introduced the InterruptFaultPage which is lower overhead since
instead of ldr+str it just turns in to a single str. We were already
allocating the space, FEXCore and the frontend signal delegator just
needed to be updated to understand the new location.

We can additionally use this in the future if we want to make deferred
async signals INSIDE the JIT only cost a single str as well.
 2024-05-10 15:31:28 -07:00
Ryan Houdek 1fde5d7fca Merge pull request #3621 from alyssarosenzweig/ra/drop-avx 
RegisterAllocationPass: drop AVX flag
 2024-05-08 11:42:53 -07:00
Ryan Houdek 10de2f83ac Merge pull request #3620 from alyssarosenzweig/ir/burn-parser 
IR: drop IRParser
 2024-05-08 11:29:37 -07:00
Alyssa Rosenzweig 9d86e11a47 RegisterAllocationPass: drop AVX flag 
RA should not depend on whether we support AVX, that's a huge layering
violation! and fortunately, it does not.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-05-08 14:26:31 -04:00
Alyssa Rosenzweig 4d503d3155 RegisterAllocationPass: drop prewritable check 
always true.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-05-08 14:24:41 -04:00
Alyssa Rosenzweig 7e663b91df IR: drop IRParser 
Aside from its own self-test, the parser is unused and should remain that way,
since it's a maintenance burden with no real benefit. Burn it.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-05-08 14:16:54 -04:00
Alyssa Rosenzweig 34fe56dfb2 DeadStoreElimination: CSE block info 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig ecf8cde5e0 DeadStoreElimination: group common logic 
slightly less obnoxious copypaste.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig 55284aad7e DeadStoreElimination: don't handle partial stores 
SRA replaces the whole contents of the destination.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig 3afc35f7b4 DeadStoreElimination: simplify 
use registers internally, not synthesized offsets

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig 1058428a51 IR: document invariant on SRA 
This lets us simplify a lot!

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig a2fc51fc7b IR: specify registers, not offsets for SRA 
SRA is fundamentally about hardware registers, not stores into a
software-defined context. So, it should take a register instead of an offset.
This makes all the unaligned special cases unrepresentable (by design).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig 1848629ba5 RegisterAllocationPass: drop aliasable check 
always true with the new ir invariants.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig b91b0e9d65 IR: infer SRA static class 
no need to stick it in the IR.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig 74489a4177 IR: remove dead SRA flags 
I don't know what these were meant for, and I don't care (-:

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig 2372c9458b ConstProp: use SetWriteCursorBefore 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-23 13:09:45 -04:00
Alyssa Rosenzweig 1a11343f34 IREmitter: add SetWriteCursorBefore helper 
This is subtle, add an ergonomic helper for it.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-23 13:09:45 -04:00
Alyssa Rosenzweig 352dcdb478 RCLSE: disable store-after-store optimization 
Functional revert of 92f31648b ("RCLSE: optimize out pointless stores"), which
reportedly regressed some titles due to RA doom. We'll revisit later, leaving in
the code for when RA is ready to light this up.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-17 14:53:11 -04:00
Paulo Matos 2b4ec88dae Whole-tree reformat 
This follows discussions from #3413.
Followup commits add clang-format file, script and blame ignore lists.
 2024-04-12 16:26:02 +02:00
Ryan Houdek 271700e9f6 Merge pull request #3568 from lioncash/const 
X87: Simplify constant loading for FLD family
 2024-04-11 00:32:26 -07:00
Lioncache 27ba66a181 IRDumper: Extend printer for NamedVectorConstant 
Makes it aware of the x87 constants.
 2024-04-09 10:13:35 -04:00
Lioncache 98841fe07a IR: Remove VectorZero 
We have LoadNamedVectorConstant that now performs this behavior while
also being more flexible.
 2024-04-08 22:42:58 -04:00
Alyssa Rosenzweig 063954c9b3 ValueDominanceValidation: rm deadcode 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-08 13:49:35 -04:00
Alyssa Rosenzweig 7b3e031678 ValueDominanceValidation: forbid crossblock liveness 
Now that we have successfully eliminated crossblock liveness from the IR we
generate, validate as much to ensure it doesn't come back. We will take
advantage of this new invariant in RA in the future.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-08 13:49:35 -04:00
Alyssa Rosenzweig a775e474d5 ValueDominanceValidation: do not validate inline constants 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-08 13:49:35 -04:00
Alyssa Rosenzweig 0e99019586 ValueDominanceValidation: actually validate 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-08 13:49:35 -04:00
Alyssa Rosenzweig 982391ba9d IR: add ShiftFlags op 
Generates flags for a variable shift as a dedicated IR op. This lets us optimize
around it (without generating control flow, relying on deferred flag infra,
etc). And it neatly solves our RA problem for shifts.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig a99c48b7a3 RedundantFlagCalculationElimination: do not eliminate if there are uses 
we'll hit this with _ShiftFlags.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig 202a60b77a Merge pull request #3549 from alyssarosenzweig/constprop/dce 
ConstProp: drop dead code
 2024-04-03 11:22:30 -04:00
Alyssa Rosenzweig e07c81a5e7 ConstProp: also negate sub -> add 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-02 13:56:59 -04:00
Alyssa Rosenzweig fa76961873 ConstProp: negate adds -> subs 
the arm ops are equiv, even though the x86 isn't (due to inverted carry).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-02 13:53:21 -04:00
Alyssa Rosenzweig b92c206db9 ConstProp: rm your deadcode 
not sure who this is supposed to be helping.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-02 13:21:48 -04:00
Alyssa Rosenzweig efff942724 ConstProp: drop my deadcode 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-02 13:21:48 -04:00
Alyssa Rosenzweig 8d32113521 ConstProp: rm relic of x86 jit 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-02 13:21:48 -04:00
Alyssa Rosenzweig bd0b5eceb8 Merge pull request #3545 from alyssarosenzweig/opt/pf-scalar 
Use scalar integer code to calculate PF
 2024-04-02 11:28:53 -04:00
Ryan Houdek e8abc88702 Merge pull request #3542 from alyssarosenzweig/ra/rep 
Eliminate xblock liveness with rep cmp/lod/scas
 2024-04-02 04:24:24 -07:00
Ryan Houdek cd9ffd2045 Merge pull request #3536 from alyssarosenzweig/ra/rcl-rcr 
OpcodeDispatcher: eliminate xblock liveness for rcl/rcr
 2024-04-01 11:44:37 -07:00
Alyssa Rosenzweig 65ec191dc1 IR: add XornShift 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-01 14:12:32 -04:00
Alyssa Rosenzweig b1ddd8cd3b Merge pull request #3541 from alyssarosenzweig/opt/clc 
optimize clc
 2024-04-01 13:51:10 -04:00
Alyssa Rosenzweig f2d001e721 Merge pull request #3543 from alyssarosenzweig/ra/dead-code 
RA: drop dead block interference code
 2024-04-01 13:51:00 -04:00
Ryan Houdek e2a095372e Merge pull request #3534 from Sonicadvance1/move_ir_defines 
FEXCore: Move nearly all IR definitions to internal
 2024-04-01 10:00:20 -07:00
Ryan Houdek 5c29c9d464 Merge pull request #3527 from Sonicadvance1/move_type_defines 
Moves FHU TypeDefines to FEXCore includes
 2024-04-01 08:57:22 -07:00
Alyssa Rosenzweig ca1ec232c9 RA: drop dead block interference code 
Unused, and new RA won't use it either. Torch it.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-03-31 20:51:11 -04:00
Alyssa Rosenzweig 4452f0acba ConstProp: optimize rmif with 0 for clc 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-03-31 20:01:44 -04:00
Alyssa Rosenzweig a70ea30c02 IR: add CondSubNZCV (ccmp) instruction 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-03-31 17:50:57 -04:00
Alyssa Rosenzweig 67baff8a57 Merge pull request #3537 from Sonicadvance1/remove_vla_ra 
RA: Removes VLA usage
 2024-03-31 14:44:37 -04:00