steam-frame/FEX-Emu--FEX
1
0 Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2026-10-16 23:00:38 +02:00
Code Issues Packages Projects Releases 67 Wiki Activity
7,837 Commits 11 Branches 71 Tags
be4fcaf65ceec1adf6cb5ae2fc29a2e03f16ecb3
Commit Graph
382 Commits
Author SHA1 Message Date
Billy Laws 51f8c83c76 Context: Add an alternative thread-oriented execute function 2023-09-22 10:12:40 -07:00
Billy Laws d641d3f61e OpcodeDispatcher: Avoid redundantly passing args to WIN32 ABI syscalls 2023-09-22 10:12:39 -07:00
Ryan Houdek 31564354b1 FEXCore: Removes vestigial Interpreter code 2023-09-21 15:49:49 -07:00
Ryan Houdek fea72ce19c Merge pull request #3120 from Sonicadvance1/more_optimal_x87 
FEXCore: Support preserve_all ABI for interpreter fallbacks
 2023-09-21 15:35:37 -07:00
Ryan Houdek 2b7e1d10ec Merge pull request #3131 from Sonicadvance1/optimize_btr 
OpcodeDispatcher: Optimize lock btr
 2023-09-21 15:06:55 -07:00
Ryan Houdek 5444810d64 Merge pull request #3132 from alyssarosenzweig/opt/orlshl 
Optimize reconstructing x87, harder
 2023-09-21 15:02:37 -07:00
Ryan Houdek 1a4d1d820b OpcodeDispatcher: Optimize lock btr 
This is an atomicFetchCLR, removes two mvn instructions that are back to
back negating the source.

We didn't have this instruction combination in InstCountCI so will be a
bit hard to see.
 2023-09-21 14:54:51 -07:00
Ryan Houdek 0ae4bbb9c5 IR: Implements support for AtomicFetchCLR 
This is the native ARM operation rather than fetchAnd. Will make an
instruction an instruction slightly more optimal.
 2023-09-21 14:54:51 -07:00
Alyssa Rosenzweig c52741c813 FEXCore: Gut interpreter 
It is scarcely used today, and like the x86 jit, it is a significant
maintainence burden complicating work on FEXCore and arm64 optimization. Remove
it, bringing us down to 2 backends.

1 down, 1 to go.

Some interpreter scaffolding remains for x87 fallbacks. That is not a problem
here.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-09-21 12:48:12 -04:00
Alyssa Rosenzweig 1596e33f58 OpcodeDispatcher: Remove pointless or 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-09-21 09:13:41 -04:00
Alyssa Rosenzweig 07d03f1610 OpcodeDispatcher: Don't opencode bfe, badly 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-09-21 09:13:41 -04:00
Alyssa Rosenzweig a8b48dcacd OpcodeDispatcher: Swap some selects 
...if it lets us use cset.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-09-21 09:13:41 -04:00
Alyssa Rosenzweig bb87b2a19d OpcodeDispatcher: Use more Orlshl 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-09-21 09:13:41 -04:00
Alyssa Rosenzweig 19eff62c77 OpcodeDispatcher: Use orlshl for FCW 
Potentially easier on the RA (bfi has a tied operand), mostly whatever here.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-09-21 08:55:25 -04:00
Mai 5fc8699db9 Merge pull request #3130 from Sonicadvance1/optimize_fsw 
OpcodeDispatcher: Optimize reconstructing FSW
 2023-09-21 08:35:16 -04:00
Ryan Houdek 5664195e49 OpcodeDispatcher: Optimize reconstructing FSW 
Minor optimization using Bfi to insert C0, C1, C2, & C3
 2023-09-21 02:07:27 -07:00
Ryan Houdek 8e9e87f631 OpcodeDispatcher: Removes non-explicit SelectCC function 
Renames the explicit sized one to `SelectCC`
Cleans up a bit of duplicated code.
 2023-09-21 01:56:38 -07:00
Ryan Houdek d588d41ab9 InterpreterFallbacks: Converts X87 and String ops to preserve_all 
This improves performance!
 2023-09-20 18:51:18 -07:00
Ryan Houdek 8aa8d597f6 Arm64: Supports jumping out of the JIT with preserve_all ABI 
This improves perferformance when jumping out of the Arm64 JIT by
reducing the number of registers we need to save.
 2023-09-20 18:51:18 -07:00
Ryan Houdek 67680d71a4 Merge pull request #3125 from Sonicadvance1/spdx_fexcore 
FEXCore: Adds SPDX identifier
 2023-09-19 17:42:07 -07:00
Ryan Houdek e4613477b1 FEXCore/Interface/Core: Adds SPDX identifier 2023-09-19 17:33:15 -07:00
Ryan Houdek d18ce59187 FEXCore/Interface/Core/JIT: Adds SPDX identifier 2023-09-19 17:33:15 -07:00
Ryan Houdek 1032224d62 FEXCore/Interface/Core/Interpreter: Adds SPDX identifier 2023-09-19 17:33:15 -07:00
Ryan Houdek 44767901fe FEXCore/Interface/Core/Dispatcher: Adds SPDX identifier 2023-09-19 17:33:15 -07:00
Ryan Houdek 1220c86573 FEXCore/Interface/Core/ArchHelpers: Adds SPDX identifier 2023-09-19 17:33:15 -07:00
Ryan Houdek 6ace406a2f FEXCore/Interface/Core/ObjectCache: Adds SPDX identifier 2023-09-19 17:33:15 -07:00
Ryan Houdek 38f1536255 FEXCore/Interface/Core/OpcodeDispatcher: Adds SPDX identifier 2023-09-19 17:33:15 -07:00
Ryan Houdek 324473651e FEXCore/Interface/Core/X86Tables: Adds SPDX identifier 2023-09-19 17:33:15 -07:00
Ryan Houdek 573148b27a FEXCore/Interface/Core/VSyscall: Adds SPDX identifier 2023-09-19 17:33:15 -07:00
Alyssa Rosenzweig 25943d1d17 OpcodeDispatcher: Sigh. 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-09-19 08:50:40 -04:00
Alyssa Rosenzweig bf03dab295 Arm64: Use csetm 
Saves some moves.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-09-19 08:50:40 -04:00
Alyssa Rosenzweig 8adfaa9aa6 OpcodeDispatcher: Use SelectCC for x87 
Better code gen and will benefit from future work.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-09-19 08:37:54 -04:00
Ryan Houdek 2ea2300408 Merge pull request #3110 from Sonicadvance1/buffered_jit_symbols 
FEXCore/JitSymbols: Buffer writes to reduce overhead
 2023-09-18 11:38:06 -07:00
Alyssa Rosenzweig df3833edbe OpcodeDispatcher: Use plain Lshl for flags 
If we have PF but no CF this simplifies the IR.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-09-18 11:01:46 -04:00
Alyssa Rosenzweig 8edcd31404 OpcodeDispatcher: Avoid inverting PF 
..if we can fold the invert into the reader.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-09-18 10:35:39 -04:00
Ryan Houdek fd1b639ad9 Merge pull request #3115 from lioncash/sqxtun 
Arm64/VectorOps: Elide moves where applicable in 128-bit VSQXTUN2
 2023-09-17 14:51:27 -07:00
Lioncache 26e4d8ad59 Arm64/VectorOps: Elide moves where applicable in 128-bit VSQXTUN2 
If the destination and lower data alias, we can
avoid needing to move into a temporary.
 2023-09-17 17:37:36 -04:00
Lioncache d54f590b14 Arm64/VectorOps: Improve handling of 128-bit vector VInsElement 
If none of the vectors alias the destination, then we can eliminate
an extra move and usage of a temporary.
 2023-09-17 16:56:23 -04:00
Lioncache 047646be6d Arm64/VectorOps: Elide moves in ASIMD VUShrNI2 if possible 
In the event the destination and lower source are the same, then
we don't need to perform any moves.
 2023-09-17 15:49:54 -04:00
Ryan Houdek 8168a49d10 Merge pull request #3112 from lioncash/assert 
Arm64/VectorOps: Assert VTMP1 and VTMP2 are sequential in VTBL2
 2023-09-17 12:40:47 -07:00
Lioncache 7f2fd4e9a0 Arm64/VectorOps: Assert VTMP1 and VTMP2 are sequential in VTBL2 
Ensures that if our temp vectors change in the future that this is
caught at compile-time rather than runtime.
 2023-09-17 15:22:39 -04:00
Lioncache 4ea9f08425 ARMEmitter: Mark index and conversion ops as constexpr 
Will be used for assertions. Also makes registers more flexible
for compile-time stuff in general.
 2023-09-17 15:19:44 -04:00
Lioncache 8ecdb341e2 Arm64/VectorOps: Fix SVE aliasing-path move in VSShr 
Seems like this was a typo from 8d11073, since we'd be moving
into a temporary and then never use it.
 2023-09-17 14:43:05 -04:00
Ryan Houdek 0c5c146fcf FEXCore/JitSymbols: Buffer writes to reduce overhead 
While this interface is usually pretty fast because it is a write and
forget operation, this has issues when there are multiple threads
hitting the perf map file at the same time. In particular this interface
becomes a bottleneck due to a locking mutex on writes in the kernel.

The situations when this bottleneck occurs is when a bunch of threads
get spawned and they are all jitting code as quickly as possible. In
particular Geekbench's clang benchmark hits this hard where each CPU
thread spends ~40% CPU time on all eight CPU threads because they are
stalled waiting for this mutex to unlock.

To work around this issue, buffer the writes a small amount. Either up
to a page-ish of data or 100ms of time. This completely eliminates
threads waiting on the kernel mutex.
- Around a page of buffer space was chosen by profiling Geekbench's
  clang benchmark and seeing how frequently it was still writing.
   - 1024 bytes was still fairly aggressive, 4096 seemed fine.
- 100ms was chosen to ensure we don't wait /too/ long to write JIT
  symbols.
   - In most cases 100ms is enough that you won't notice the blip in
     perf.

One thing of note is that with profiling enabled and checking the time
on every JIT block still ends up with 2-3% CPUtime in vdso
clock_gettime. We can improve this by using the cyclecounter directly
since that is still guaranteed to be monotonic. Maybe we'll come back to
that if it is actually an issue here.
 2023-09-16 17:52:46 -07:00
Ryan Houdek ad8b0c673f Merge pull request #3109 from lioncash/shlx 
OpcodeDispatcher: Improve output of SHLX/SHRX/SARX
 2023-09-15 18:49:36 -07:00
Ryan Houdek e574cfe681 Merge pull request #3108 from lioncash/mulx 
OpcodeDispatcher: Improve output of MULX
 2023-09-15 18:09:02 -07:00
Lioncache e9be291cec OpcodeDispatcher: Improve output of SHLX/SHRX/SARX 
We can remove some unnecessary moves for the 32-bit cases and
collapse the operations down to a single instruction.
 2023-09-15 21:05:50 -04:00
Lioncache d4f87c7db1 OpcodeDispatcher: Improve output of MULX 
We can cut down on a few of the generated moves. For
the case where both destinations alias one another,
we can just calculate the high part instead of both of them.
 2023-09-15 20:52:02 -04:00
Lioncache b0c8ff0ea6 Arm64/ALUOps: Remove spills in PEXT 
Reduces the number of emitted instructions for a
corresponding PEXT instruction.

We no longer spill for this IR op.
 2023-09-15 19:39:51 -04:00
Lioncache be90e76422 Arm64/ALUOps: mov in the case of full 32-bit/64-bit BFE 
Allows register-renaming mechanisms to be invoked more frequently
 2023-09-15 17:38:01 -04:00