Alyssa Rosenzweig
adc709db2f
OpcodeDispatcher: drop remnants of deferred flags
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-07-05 17:22:41 -04:00
Alyssa Rosenzweig
395573720d
OpcodeDispatcher: drop pointless flag defers for shifts
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-07-05 16:24:54 -04:00
Alyssa Rosenzweig
0e62759d24
OpcodeDispatcher: stop deferring logical
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-07-05 16:24:54 -04:00
Alyssa Rosenzweig
926b6c3117
OpcodeDispatcher: don't defer mul flags
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-07-05 16:24:54 -04:00
Alyssa Rosenzweig
c9f9304ba5
OpcodeDispatcher: stop deferring obscure bitwise
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-07-05 16:24:54 -04:00
Alyssa Rosenzweig
fabd6be5af
OpcodeDispatcher: drop SUB defer
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-07-05 16:24:54 -04:00
Ryan Houdek
f6ec99bede
OpcodeDispatcher: Fixes rotates with zero not zero extending 32-bit result
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For all the 32-bit rotates (except for RORX) we were failing to zero
extend the 32-bit result to the destination register when the rotate was
masked to zero.
Ensure we do this.
2024-07-04 14:35:42 -07:00
Ryan Houdek
0d06e3e47d
Revert "OpcodeDispatcher: add cache"
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This reverts commit 46676ca376
2024-07-02 20:24:57 -07:00
Ryan Houdek
78aee4d96e
Revert "IR: drop RCLSE"
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This reverts commit a5b24bfe4c
2024-07-02 20:21:59 -07:00
Ryan Houdek
a451420911
Merge pull request #3783 from Sonicadvance1/optimize_vector_zeroregister
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OpcodeDispatcher: Optimize x86 canonical vector zero register
2024-07-01 18:57:31 -07:00
Ryan Houdek
cffae9cb0f
AVX128: Minor optimization to 256-bit vpshufb
2024-06-30 13:41:03 -07:00
Ryan Houdek
7d05610da7
OpcodeDispatcher: Optimize x86 canonical vector zero register
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The canonical way to generate a zero register vector in x86 is to xor
itself. Capture this can convert it to canonical zero register instead.
Can get zero-cycle renamed on latest CPUs.
2024-06-29 22:21:53 -07:00
Ryan Houdek
f2f90eeb82
FEXCore: Make more distinctions between host register size and guest vector register size
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We can support a few combinations of guest and host vector sizes
Host: 128-bit or 256-bit
Guest: 128-bit or 256-bit
The typical case is Host = 128-bit and Guest = 256-bit now that AVX is
implemented.
On 32-bit this changes to Host=128-bit and Guest=128-bit because we
disable AVX.
In the vixl simulator 32-bit turns in to Host=256-bit and Guest=128-bit.
And then in the vixl sim 64-bit turns in to Host=256-bit and
Guest=256-bit.
We cover all four combinations of guest and host vector register sizes!
Fixes a few assumptions that SVE256 = AVX256 basically.
2024-06-28 13:05:52 -07:00
Alyssa Rosenzweig
196a0531e0
OpcodeDispatcher: optimize nzcv with asimd masked load/store
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-06-27 10:37:06 -04:00
Ryan Houdek
3a89df9bed
AVX128: Implement support for F16C
2024-06-26 14:05:12 -07:00
Ryan Houdek
a4fa3a460e
OpcodeDispatcher: Implement AVX gathers with SVE256
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Just to ensure we still have feature parity.
2024-06-26 16:00:53 -04:00
Ryan Houdek
77ba708933
AVX128: Implement support for gather load instructions
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This is the last family of instructions that we needed to implement for
AVX2 to be properly advertised!
2024-06-26 16:00:53 -04:00
Alyssa Rosenzweig
d1d41f5645
Merge pull request #3763 from alyssarosenzweig/rclse/less-aggressive
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Remove RCLSE
2024-06-26 15:14:14 -04:00
Ryan Houdek
94fd100fc7
Merge pull request #3719 from lioncash/f16c
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OpcodeDispatcher: Handle F16C operations
2024-06-26 12:12:13 -07:00
Lioncache
cd5a809ec9
OpcodeDispatcher: Handle VCVTPS2PH
2024-06-26 15:05:03 -04:00
Lioncache
045a8efbeb
OpcodeDispatcher: Handle VCVTPH2PS
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Fairly straightforward, since we already have handling for half-float conversions.
2024-06-26 15:05:00 -04:00
Alyssa Rosenzweig
a5b24bfe4c
IR: drop RCLSE
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-06-26 14:49:05 -04:00
Alyssa Rosenzweig
46676ca376
OpcodeDispatcher: add cache
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-06-26 14:49:05 -04:00
Ryan Houdek
832b247fc1
SVE258: Implement support for FMA3
2024-06-25 11:24:46 -07:00
Ryan Houdek
0e8b53d566
AVX128: Implement FMA3 instructions
2024-06-25 11:23:50 -07:00
Ryan Houdek
7069643ae6
AVX128: Implement support for VPCLMULQDQ
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This is just the 128-bit version twice.
2024-06-25 10:03:33 -04:00
Ryan Houdek
34272fc134
AVX128: Implement support for vperm{d,ps}!
2024-06-25 10:03:33 -04:00
Ryan Houdek
1d41002dfe
AVX128: Implement support for variable vpermil{ps,pd}
2024-06-25 10:03:33 -04:00
Ryan Houdek
563bf342d5
AVX128: Implement support for vptest
2024-06-25 10:03:33 -04:00
Ryan Houdek
efd5fabb95
AVX128: Implement support for vtest{ps,pd}
2024-06-25 10:03:33 -04:00
Ryan Houdek
c1da525110
AVX128: Implement support for vperm2{f128,i128}
2024-06-25 10:03:33 -04:00
Ryan Houdek
64cce7c6fa
AVX128: Implement support for xsave/xrstor
2024-06-25 10:03:33 -04:00
Ryan Houdek
4544e5b51f
AVX128: Implement support for vblend{ps,pd}/vpblendvb
2024-06-25 10:03:33 -04:00
Ryan Houdek
eb3e314946
AVX128: Implement support for vmaskmovdqu
2024-06-25 10:03:33 -04:00
Ryan Houdek
8b65c3de10
AVX128: Implement vmaskmov{ps,pd}, vpmaskmov{d,q} using SVE2 gather loadstores.
2024-06-25 10:03:33 -04:00
Ryan Houdek
c2beb27a9d
AVX128: Implement support for vpalignr
2024-06-25 10:03:33 -04:00
Ryan Houdek
05fdec9e72
AVX128: Implement support for vmpsadbw
2024-06-25 10:03:33 -04:00
Ryan Houdek
e8e3c95349
AVX128: Implement support for vpsadbw
2024-06-25 10:03:33 -04:00
Ryan Houdek
a87fa3f246
AVX128: Implement support for vpshufb
2024-06-25 10:03:33 -04:00
Ryan Houdek
b31ad523f5
AVX128: Implement support for hsub{ps,pd}
2024-06-25 10:03:33 -04:00
Ryan Houdek
34bce540ff
AVX128: Implement support for vpblendw/vpblendd/vblendps/vblendpd
2024-06-25 10:03:33 -04:00
Ryan Houdek
8ea38e1d80
AVX128: Implement support for vpmaddwd
2024-06-25 10:03:33 -04:00
Ryan Houdek
ce591a9541
AVX128: Implement support for vpmaddubsw
2024-06-25 10:03:33 -04:00
Ryan Houdek
a48c65cd65
AVX128: Implement support for vphaddsw
2024-06-25 10:03:33 -04:00
Ryan Houdek
c283f80f48
AVX128: Implement support for vhaddpd/vphadd{w,d}
2024-06-25 10:03:33 -04:00
Ryan Houdek
d6bf276b5a
AVX128: Implement support for imm vpermil{ps,pd}
2024-06-25 10:03:33 -04:00
Ryan Houdek
96a51650b1
AVX128: Implement support for vshuf{ps,pd}
2024-06-25 10:03:33 -04:00
Ryan Houdek
f35a9c74a2
AVX128: Implement support for vpshuf{lw,hw,d}
2024-06-25 10:03:33 -04:00
Ryan Houdek
e2457943f5
AVX128: Implement support for vperm{q,pd}
2024-06-25 10:03:33 -04:00
Ryan Houdek
a05644172a
AVX128: Implement support for vdd{ps,pd}
2024-06-25 10:03:33 -04:00
Alyssa Rosenzweig