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Code Issues Packages Projects Releases 67 Wiki Activity
493 Commits 11 Branches 71 Tags
a97c2c8bb3fb32ecbdd5261bfe60bf4d0006bf2a
Commit Graph
124 Commits
Author SHA1 Message Date
Ryan Houdek a97c2c8bb3 Adds MMX decoding support to the frontend 2020-03-27 18:07:57 -07:00
Stefanos Kornilios Mitsis Poiitidis 84743796a5 Merge pull request #67 from Sonicadvance1/more_cvt 
Implements two more CVT instructions
 2020-03-23 00:39:59 +02:00
Stefanos Kornilios Mitsis Poiitidis d0667452e6 Merge pull request #66 from Sonicadvance1/pmul 
Implements PMULLW
 2020-03-23 00:39:49 +02:00
Ryan Houdek 33e68cf0c4 Implements PADDB in OpDispatcher 2020-03-22 13:07:25 -07:00
Ryan Houdek eeebfeaec1 Implements two more CVT instructions 
CCVTSS2SI and CVTTPD2DQ
 2020-03-22 13:03:34 -07:00
Ryan Houdek ad71b4de94 Implements PMULLW in OpDispatcher 
Renames the PMULL function that does PMUL to larger element to have the distinction between the two
 2020-03-22 13:00:36 -07:00
Ryan Houdek f4dc6ee1ce Adds vector multiply op to LLVM JIT 2020-03-22 13:00:36 -07:00
Stefanos Kornilios Mitsis Poiitidis 013ac22744 Merge pull request #62 from Sonicadvance1/vector_mul 
Implement vector integer multiply IR ops
 2020-03-22 09:01:35 +02:00
Stefanos Kornilios Mitsis Poiitidis 7930712ef2 Merge pull request #63 from Sonicadvance1/vector_ftozs 
Implements Vector_FTOZS op in x86 JIT
 2020-03-22 09:01:21 +02:00
Stefanos Kornilios Mitsis Poiitidis 7989a22802 Merge pull request #53 from Sonicadvance1/fix_flag_setting 
Implements and fixes flag setting in a few instructions
 2020-03-22 09:01:08 +02:00
Ryan Houdek f89ef01578 Implements the COMISS instructions 
These are fairly popular so not having them around is causing headaches.
We will really want these in the future to use the host register, btu
that is more time consuming than I want to dedicate to at the moment.

So the FCMP instruction must be told which flags to generate up front,
then it generates the flags in to a GPR which are then tracked and
pulled out with a specific IR op.

This can be augmented in the future to more easily RA the host flag
register
 2020-03-21 22:52:46 -07:00
Ryan Houdek c94102051c Implements Vector_FTOZS op in x86 JIT 2020-03-21 20:58:53 -07:00
Ryan Houdek 2133a1755d Implement vector integer multiply IR ops 2020-03-21 20:56:54 -07:00
Ryan Houdek b93848c343 Removes sarx usage in the x86 JIT 2020-03-21 12:44:27 -07:00
Stefanos Kornilios Mitsis Poiitidis f9b7eff7c6 Merge pull request #58 from Sonicadvance1/instruction_fixes 
Fixes for SQRTPD, SQRTPS, RSQRTPS
 2020-03-21 09:31:00 +02:00
Stefanos Kornilios Mitsis Poiitidis c4cc36d23b Merge pull request #54 from Sonicadvance1/threaded_compile_workaround 
Throws a mutex in CompileBlock until we properly handle threaded compilation.
 2020-03-21 09:27:06 +02:00
Ryan Houdek 6de60bea70 Fixes FRSQRT in AArch64 
fmov (vector, immediate, broadcast) keys register size based on the
float/double constant passed in

So since 1.0f was missing the f, it was passed as a double, duplicating
64bit doubles rather than 32bit floats
 2020-03-20 19:49:05 -07:00
Ryan Houdek 2bc7c28a9c Fixes AArch64 ROL implementation 
In the case that RA does Dst = Src[1] then we would have overwrote our
shift value. Move the negation to the top of the 8bit and 16bit ROL to
make sure that doesn't happen
 2020-03-20 18:58:39 -07:00
Ryan Houdek 76d67812ed Implements 64bit RSQRT and fixes vector 32bit RSQRT in the x86 JIT. 2020-03-20 18:14:44 -07:00
Ryan Houdek ba71271982 Implements SQRTPS in OpDispatcher 2020-03-20 18:14:44 -07:00
Ryan Houdek 24159b969c Fixes RSQRTPS x86 tables 2020-03-20 18:14:39 -07:00
Ryan Houdek 8e06765101 Throws a mutex in CompileBlock until we properly handle threaded compilation. 
This is purely a workaround until it gets implemented correctly
 2020-03-20 12:25:14 -07:00
Ryan Houdek c44da5d3eb Implements and fixes flag setting in a few instructions 
A few instructions were missing flag setting entirely or were generating
wrong flags
  - ROL, ROR, SHL, SHR, ASHR, SHLD, SHRD, CMPXCHG

This fixes those instructions and removes a few outdated comments
Specifically noticed when trying to run xcalc, it was using the flag
results from SHL for something and crashed without flag setting.

Unit tests for RFLAG setting instructions is still forthcoming
 2020-03-20 12:22:00 -07:00
Ryan Houdek a059fc1943 Adds hypervisor CPUID function 
4000'0000h is the hypervisor CPUID information leaf, can just return all
zeroes to imply we aren't running under a hypervisor

EAX: The maximum input value for CPUID supported by the hypervisor.
     - We return zero here to signify no Hypervisor
EBX, ECX, EDX: Vedor ID signature

CPUID 4000'0001h - 4000'000Fh is reserved for hypervisor, which we don't
need to expose since we return zero in EAX
 2020-03-20 12:06:01 -07:00
Ryan Houdek 55a2c3ca99 Merge pull request #41 from Sonicadvance1/fix_llvm9 
LLVM 9 fixes
 2020-03-18 11:05:40 -07:00
Ryan Houdek fc452de973 Some more fixes for LLVM picked up from the AArch64 side 
AArch64 is a bit more picky when mixing vector and scalar ops
 2020-03-17 19:28:17 -07:00
Ryan Houdek 2e0851975f Makes sure LLVM on AArch64 can read the cycle counter 2020-03-17 19:28:08 -07:00
Ryan Houdek d6fb1f2d17 Make sure OpDispatcher is using explicit scalar operations 
LLVM specifically gets really picky if you mix vector and scalar ops.
Additionally AArch64 seems to be even pickier than x86 for this
 2020-03-17 19:27:58 -07:00
Ryan Houdek 94cf11068c Makes sure Interpreter zeros the upper 64bits when doing Double->Float 2020-03-17 19:27:50 -07:00
Ryan Houdek 90c4b3dae7 Merge pull request #33 from Sonicadvance1/minor_x86_vsqxtun 
Minor optimization in vsqxtun for x86
 2020-03-17 17:01:18 -07:00
Ryan Houdek 388e723c78 Fixes shift ops in LLVM9 
These don't need to operate at 128bit, just one size larger than
incoming.
This is because of 8bit and 16bit shifts rely on 32bit size masking
rather than 8bit and 32bit, so they have to shift at a larger size due
to ensure correct behaviour(that is not undefined).
LLVM-8 worked with the previous behaviour but broke with LLVM-9.
So changing it to this slightly smarter code gen.
 2020-03-17 13:52:23 -07:00
Ryan Houdek 16382c4202 Fixes Scalar FCMP in LLVM9 
LLVM9 is a bit more strict when mixing scalar and vector ops.
Was causing crashes inside of LLVM when mixing a vector source with a
scalar source
 2020-03-17 13:51:07 -07:00
Ryan Houdek 8ea266e10f Implements the new IR ops in the CPU backends 2020-03-17 13:50:37 -07:00
Ryan Houdek 4692a761b6 Implements two new IR Op codes 
Extracts a vector element to a scalar value
Inserts a scalar element in to a vector
 2020-03-17 13:49:47 -07:00
Stefanos Kornilios Mitsis Poiitidis 2993e4dab6 Merge pull request #37 from Sonicadvance1/unittests/bt_reg 
Unit tests and fixes for BT ops with GPR destination
 2020-03-17 19:43:44 +02:00
Ryan Houdek 7ba9aef304 Fixes AArch64 LLVM intrinsic typo 
arch64 != aarch64
 2020-03-17 09:35:39 -07:00
Ryan Houdek 469935e5b8 Fixes x86-64 JIT using invalid movzx 
Found with BT test ops
 2020-03-17 09:26:52 -07:00
Ryan Houdek 21e9ec5f8a Fixes BT ops masking bit selection on GPR destination 
When the destination is a GPR instead of a memory location then the
source bitselect register is masked by the size of the operation
 2020-03-17 09:25:21 -07:00
Ryan Houdek a16638844f Merge pull request #31 from Sonicadvance1/fix_llvm_jit 
Implements all the ops missing in the LLVM JIT
 2020-03-17 09:22:44 -07:00
Ryan Houdek 0a87cbf9d9 Merge pull request #30 from Sonicadvance1/aarch64_jit_fixes 
Get AArch64 JIT to feature parity of the x86 JIT
 2020-03-17 09:22:34 -07:00
Ryan Houdek 4718493d6c Merge pull request #27 from Sonicadvance1/fixes_jit_x86_#2 
x86-64 JIT unit test fixes
 2020-03-17 09:22:17 -07:00
Ryan Houdek 9a54578fd8 Minor optimization in vsqxtun for x86 
No need to zero the register when we are going to logical shift the
upper 64bits to the lower 64bits anyway
 2020-03-15 22:32:23 -07:00
Ryan Houdek 568af31578 Implements all the ops missing in the LLVM JIT 
Lets the LLVM pass the unit tests as well as the interpreter and other
JITs
 2020-03-15 22:30:11 -07:00
Ryan Houdek 1cf60f43cb [AArch64] Implements vector integer length and narrow ops 2020-03-15 00:54:33 -07:00
Ryan Houdek 99d95d5bca [AArch64] Implements float conversion ops 2020-03-15 00:53:49 -07:00
Ryan Houdek deac8d5a75 [AArch64] Implements vector float compare ops 2020-03-15 00:52:43 -07:00
Ryan Houdek 823c803142 [AArch64] Fixes GPR<->FPR conversion moves 2020-03-15 00:45:50 -07:00
Ryan Houdek 702473d3a5 [AArch64] Implements vector shift by immediate ops 2020-03-15 00:44:35 -07:00
Ryan Houdek 4212d177a3 [AArch64] Fixes VSLI/VSRI for byte shifts larger than the register. Needs to zero the reg 2020-03-15 00:44:15 -07:00
Ryan Houdek 35317d0e8a [AArch64] Fixes and implements vector shift ops 2020-03-15 00:43:06 -07:00