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Code Issues Packages Projects Releases 67 Wiki Activity
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Commit Graph
401 Commits
Author SHA1 Message Date
Ryan Houdek e9867ca35a Revert "FEXCore: Change yield implementation to use wfe" 
This reverts commit e53f3969e9.
 2024-12-06 17:02:27 -08:00
Paulo Matos 1d3ce30e50 Generate SVE for 80bit load/stores when possible 
Fixes #4166.
 2024-12-06 10:15:29 +01:00
Paulo Matos fcbf0de05a Enable RA of SVE Predicate Registers 2024-12-02 18:35:31 +01:00
Ryan Houdek 9b6cc8f7e0 IR: Convert OpSize over to enum class 
NFC

Do the final mopping up to convert the OpSize enum to an enum class!
 2024-10-29 16:52:16 -07:00
Ryan Houdek 82f936cb6d IR: Converts base IR operations to store OpSize sizes 
NFC

Finally converts the IR operations themselves to store the OpSize for
the IR operation size and element sizes.

This also finally, FINALLY, converts that remaining `_Constant` helper
to stop using a size field that is specified in bits rather than bytes
like all the other IR op handlers. That thing was so confusing and now
it's gone.
 2024-10-28 21:26:59 -07:00
Ryan Houdek 460a21625e JIT: Remove implicit OpSize conversions 
NFC
 2024-10-28 19:48:40 -07:00
Ryan Houdek b31e4a3c27 JIT: Moves Arm64 JIT up one folder 
We have only one JIT, there is no reason to subfolder this. Move it up
one folder.

NFC
 2024-10-25 18:44:20 -07:00
Ryan Houdek 048e967546 FEXCore: Adds support for CPU Index through TPIDRRO 2024-10-25 15:07:57 -07:00
Alyssa Rosenzweig 698abec25c JIT: drop FindMSB zero handling 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-22 13:29:47 -04:00
Alyssa Rosenzweig 1578f5ed47 JIT: drop FindLSB masking 
consequence of the UB

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-22 13:29:47 -04:00
Alyssa Rosenzweig 80d7b5a5c9 JIT: drop FindLSB zero handling 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-22 13:29:47 -04:00
Paulo Matos 49087007be Implement NZCVSelectV for selection on FPRs 
Behaves like NZCVSelect for FPRs.
 2024-10-17 08:42:50 +02:00
Ryan Houdek e53f3969e9 FEXCore: Change yield implementation to use wfe 
According to
https://github.com/rust-lang/rust/commit/c064b6560b7ce0adeb9bbf5d7dcf12b1acb0c807
turns out that the arm yield instruction is effectively a nop on all
reasonably new CPUs.
Instead switch over to wfe because it matches x86 `PAUSE` semantics more
closely.
 2024-10-15 05:50:26 -07:00
Ryan Houdek 24211f8523 FEXCore: Move ThunksHandler class to FEXLoader 
With as little changes as possible, because this is fairly tricky.
 2024-09-27 15:48:31 -07:00
Alyssa Rosenzweig 33186b803d JIT: fix scalar fmax on non-AFP platforms 
NaN and signed zero handling was busted.  Pretty nasty.

Fixes the following Vulkan CTS test run under emulation without thunking with a clang-built Mesa:

  dEQP-VK.spirv_assembly.instruction.graphics.float_controls.fp32.generated_args.denorm_nmax_nan_flush_to_zero_vert

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-09-22 12:14:21 -04:00
Alyssa Rosenzweig bb1d7d0750 JIT: rm broken dead code 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-09-22 12:14:21 -04:00
Ryan Houdek 34f2bce203 FEXCore: Remove Context header include when unneeded 
This is one of the most expensive headers in FEX, averaging 1.2 seconds
of compile time per include.
We include this header 31 times around the project. Remove
the five instances where it is unused to help this issue. Next step
would be to make the header lighter if possible.
 2024-09-09 17:43:35 -07:00
Ryan Houdek e6025cc087 Arm64: Fix warning 
This variable is only used in a log message no, so move it there.
 2024-09-08 11:15:46 -07:00
Alyssa Rosenzweig 67c751d3e5 JIT: always use 64-bit moves for SRA 
I see no reason not to. Simpler code and it's slightly faster on Firestorm.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-09-08 13:02:57 -04:00
Ryan Houdek 1c59bfeb9f Merge pull request #4027 from alyssarosenzweig/opt/global-flag 
Global flag optimizations
 2024-09-08 09:42:18 -07:00
Ryan Houdek 59643db331 CPUBackend: Remove unused functions 
Some of these were bad ideas, some ideas were something we effectively
grew out of.
 2024-09-07 08:07:00 -07:00
Alyssa Rosenzweig 50a3ca0d6d IR: introduce dedicated PF/AF instructions 
this makes reasoning about them a little easier, e.g. for flags.  about 1% win
in nodejs.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-09-07 10:59:05 -04:00
Alyssa Rosenzweig e9ab514962 IR: push parity evaluation down 
so we can optimize it globally

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-09-07 08:26:04 -04:00
Alyssa Rosenzweig 4eb0948451 IR: push down AXFLAG lowering 
so we can get the new axflag optimizations on billy's x13s.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-09-07 08:26:04 -04:00
Alyssa Rosenzweig 8d9f19bd73 IR: add TestZ op 
more optimized than TestNZ if we don't care about the sign bit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-09-07 08:26:04 -04:00
Alyssa Rosenzweig 6d4693cbc1 IR: fix scalar FMA tied sources 
needs to be modelled explicitly or else we lose information when translating

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-09-04 07:42:44 -04:00
Ryan Houdek b19440c78f Arm64: Ensure 256-bit operations always assert without 256-bit SVE 
Our JIT will happily consume incorrectly formed 256-bit vector operations in a lot of cases when the host CPU doesn't support 256-bit SVE.
This is what caused the bug in #4006. For every vector operation that
can consume a 256-bit size, add an assert that always checks if 256-bit
SVE is supported in those cases.

This will ensure that #4006 doesn't happen again.
 2024-08-25 18:16:31 -07:00
Alyssa Rosenzweig ce8e6e5c0c OpcodeDispatcher: optimize adc 0 
clang generates this.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-22 10:51:06 -04:00
Alyssa Rosenzweig d53e689e22 IR: model tbz/tbnz 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-21 17:52:22 -04:00
Alyssa Rosenzweig d0e040514f IR: add LoadContextPair 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:31:19 -04:00
Alyssa Rosenzweig 850c027d52 IR: add AllocateFPR 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:31:19 -04:00
Alyssa Rosenzweig 5df90563e2 IR: add LoadMemPair 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:31:19 -04:00
Alyssa Rosenzweig 7a489d18c6 IR: add StoreMemPair 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:31:19 -04:00
Alyssa Rosenzweig 1db092e96f IR: add StoreContextPair 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:31:19 -04:00
Ryan Houdek 689b461d7b Merge pull request #3984 from Sonicadvance1/atomic_tso_subchecks 
FEXCore: Splits up atomic enablement checks
 2024-08-20 15:16:54 -07:00
Ryan Houdek 9c8438f264 FEXCore: Splits up atomic enablement checks 
PR #3980 is adding a feature to merge loadstores in to paired
loadstores, but it was using the incorrect atomic check to determine if
it can safely merge them or not. It was using the GPR atomic check
instead of the vector atomic check. While this would improve performance
on Apple Silicon with its hardware TSO implementation, it would have had
zero impact on Cortex and Oryon.

Instead split out the three config options to live as a boolean check in
the ContextImpl similar to how we disable "AtomicTSOEmulation". Removing
the various configs in the JIT and CPUID so that it queries from the
same context. This makes it clearer that if you are wanting the current
active configuration for memcpy, vector, or general atomic TSO
emulation, you should query one of those three getters.

This also fixes a weird edge case bug in the arm64 JIT where you could
have TSO emulation disable, but still have vector TSO enabled partially.
Just because half a config wasn't checked in {Load,Store}MemTSO for
vectors. If the global "TSOEnabled" option is disabled then TSO should
always be disabled.

Alyssa will be able to pull this in to #3980 once merged and get the
performance uplift on Cortex and Oryon, since our default configuration
is to have vector and memcpy TSO emulation disabled.
 2024-08-20 14:34:34 -07:00
Ryan Houdek caf7ad53e6 Arm64: Allow directly correlating an ARM register back to an x86 register 
Fixes a bug that is getting introduced in to #3955 when it rearranged
register allocation.
 2024-08-20 14:17:13 -07:00
Alyssa Rosenzweig 7de6a5cb07 OpcodeDispatcher: optimize rotate flags 
introduce an IR op for it so we can reason about flags across rotate
instructions easily.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-19 10:40:53 -04:00
Ryan Houdek ef4c4f6e9b FEXCore: Disable vixl linking if vixl disasm or simulator is disabled 
This was mostly there, just needed to remove some extraneous headers and
only insert vixl in to the library list if the options were enabled.
 2024-08-16 07:29:41 -07:00
Ryan Houdek 933c65d805 Merge pull request #3956 from alyssarosenzweig/opt/pop-return 
small optimizations for returns
 2024-08-15 03:30:23 -07:00
Ryan Houdek df0ecad15b Merge pull request #3933 from bylaws/arm64-suspend 
Support cooperative suspend on ARM64EC
 2024-08-15 01:22:28 -07:00
Alyssa Rosenzweig 2dc92c122e BranchOps: micro-optimize ExitFunction 
this should be slightly faster on Firestorm and no worse on recent cortex

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 16:59:34 -04:00
Ryan Houdek aa5d2ff31c Merge pull request #3951 from alyssarosenzweig/opt/pops 
Add a hack for multiple destinations & make good use of it
 2024-08-14 12:03:00 -07:00
Alyssa Rosenzweig 200c6c054f IR: introduce POP operation 
rmw on a source, kind of terrible.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig bc0927b7b1 JIT: optimize moves for cmpxchg 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig 64a45c0d29 IR: remove pairs 
They're now unused. And won't be missed.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig cab02be637 IR: remove unused pair create/extract 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig 74f341bc0e IR: remove pair from cpuid 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig feaa1af1a8 IR: remove pair from XGetBV 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig a9c26cbf71 IR: add coalescing heuristics for pair replacements 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00