 Ryan Houdek
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a05644172a
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AVX128: Implement support for vdd{ps,pd}
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2024-06-25 10:03:33 -04:00 |
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Ryan Houdek
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cc168ce0fb
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VectorOps: Restructure DPPOpImpl. This will get reused by AVX128
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2024-06-25 10:03:33 -04:00 |
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Alyssa Rosenzweig
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18574f3cf1
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OpcodeDispatcher: extract VPERMILRegOpImpl
for avx
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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2024-06-25 10:03:33 -04:00 |
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Alyssa Rosenzweig
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665215ab47
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OpcodeDispatcher: extract PTestOpImpl
for avx128
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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2024-06-25 09:52:48 -04:00 |
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Alyssa Rosenzweig
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6009f36403
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OpcodeDispatcher: extract VPERMDIndices
and rename things accordingly.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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2024-06-25 09:46:17 -04:00 |
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Alyssa Rosenzweig
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2580efda0d
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OpcodeDispatcher: tweak VTestOp signature
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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2024-06-25 09:46:17 -04:00 |
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Alyssa Rosenzweig
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21c6986dc7
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OpcodeDispatcher: tweak HSUBPOpImpl
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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2024-06-24 18:21:08 -04:00 |
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Alyssa Rosenzweig
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635720fe12
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OpcodeDispatcher: tweak PHADDSOpImpl signature
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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2024-06-24 18:21:08 -04:00 |
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Ryan Houdek
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702ecf7637
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AVX128: Implement support for round{ss,sd}
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2024-06-24 15:19:08 -04:00 |
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Ryan Houdek
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0595f1e044
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AVX128: Implement support for vround{ps,pd}
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2024-06-24 15:19:08 -04:00 |
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Ryan Houdek
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cebb032bd3
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AVX128: Implement support for vphminposuw
Reuses the non-AVX implementation since it only operates on 128-bits.
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2024-06-24 15:19:08 -04:00 |
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Ryan Houdek
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8e32763ada
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AVX128: Implements support for AVX string ops
Reuses the implementation from the SSE4.2 implementation, just
explicitly zeroes the hardcoded YMM0's upper 128-bits.
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2024-06-24 15:19:08 -04:00 |
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Ryan Houdek
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7532337231
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AVX128: Implements support for vector AES instructions
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2024-06-24 15:19:08 -04:00 |
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Ryan Houdek
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4a66d4570e
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AVX128: Implement support for a trinary operation with a passed in vector
Will be used for AES operations
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2024-06-24 15:19:08 -04:00 |
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Alyssa Rosenzweig
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6f5e99d47d
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OpcodeDispatcher: factor out TranslateRoundType
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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2024-06-24 15:19:08 -04:00 |
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Alyssa Rosenzweig
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9ee9f5bddd
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OpcodeDispatcher: tweak VectorRoundImpl signature
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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2024-06-24 15:14:55 -04:00 |
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Ryan Houdek
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d29139d88a
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AVX128: Implement support for vextract{i,f}128
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2024-06-24 14:27:19 -04:00 |
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Ryan Houdek
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317575ba99
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AVX128: Implement support for cvtdq2{ps,pd}
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2024-06-24 14:27:19 -04:00 |
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Ryan Houdek
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d4f2638a2e
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AVX128: Implement support for cvt{t,}pd2pq
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2024-06-24 14:27:19 -04:00 |
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Ryan Houdek
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b67d9be227
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AVX128: Implement support for vcvt{pd2ps,ps2pd}
Fairly complex set of instructions due to the edge cases.
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2024-06-24 14:27:19 -04:00 |
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Ryan Houdek
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d52add8fad
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AVX128: Implement support for vcvt{ss2sd,sd2ss}
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2024-06-24 14:27:19 -04:00 |
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Ryan Houdek
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aa9159d25c
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AVX128: Implement support for vpmulh{u,}w
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2024-06-24 14:27:19 -04:00 |
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Ryan Houdek
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94c777259e
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AVX128: Implements support for vpmulhrsw
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2024-06-24 14:27:19 -04:00 |
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Ryan Houdek
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c9f8fa5662
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AVX128: Implement support for vpmul{u,}dq
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2024-06-24 14:27:19 -04:00 |
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Ryan Houdek
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64ee6b119e
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AVX128: Implement support for vaddsubp{s,d}
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2024-06-24 14:27:19 -04:00 |
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Ryan Houdek
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d2ec9a8936
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AVX128: Implement support for vpsubsw
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2024-06-24 14:27:19 -04:00 |
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Ryan Houdek
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2a927453f7
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AVX128: Implement support for vphsub{w,d}
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2024-06-24 14:27:19 -04:00 |
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Ryan Houdek
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c19d489c9a
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AVX128: Implement support for vinsertps
This one actually reuses the core base implementation which is nice.
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2024-06-24 14:27:19 -04:00 |
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Ryan Houdek
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6012eb051b
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AVX128: Implement support for vinsert{f128,i128}
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2024-06-24 14:27:19 -04:00 |
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Alyssa Rosenzweig
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3974746473
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OpcodeDispatcher: tweak PHSUBOpImpl
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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2024-06-24 14:14:23 -04:00 |
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Alyssa Rosenzweig
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e1bcdcf387
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OpcodeDispatcher: tweak PHSUBSOpImpl signature
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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2024-06-24 14:14:23 -04:00 |
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Alyssa Rosenzweig
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fd5fbddae9
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OpcodeDispatcher: tweak PMULLOpImpl for avx128
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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2024-06-24 14:14:23 -04:00 |
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Alyssa Rosenzweig
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8ff72beddb
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OpcodeDispatcher: tweak PMULHRSWOpImpl signature for avx128
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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2024-06-24 14:14:23 -04:00 |
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Alyssa Rosenzweig
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cba5f7877b
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OpcodeDispatcher: tweak ADDSUBPOpImpl signature for AVX128
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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2024-06-24 14:14:23 -04:00 |
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Alyssa Rosenzweig
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9d7e9fd9fc
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OpcodeDispatcher: add AVX128_Zext helper
should let us clean up a lot.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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2024-06-24 14:14:23 -04:00 |
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Ryan Houdek
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9c531d97b0
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AVX128: Implements the various vector shift instructions
These are very closely related to each other so it makes sense to
implement the roughly three different families in one commit.
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2024-06-24 09:20:19 -04:00 |
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Ryan Houdek
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abdcaa7c86
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AVX128: Implement support for vpinsr{b,w,d,q}
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2024-06-21 15:53:52 -04:00 |
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Ryan Houdek
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ad122cf463
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AVX128: Implement support for vpmovmskb
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2024-06-21 15:53:52 -04:00 |
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Ryan Houdek
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b58a57d225
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AVX128: Implement support for vmovmskp{s,d}
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2024-06-21 15:53:52 -04:00 |
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Ryan Houdek
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28d679de98
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AVX128: Implement support for vpmov{s,z}{b,w,d}{w,d,q}
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2024-06-21 15:53:52 -04:00 |
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Ryan Houdek
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d1dd055e6a
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AVX128: Implement support for vpextr{b,w,d,q}
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2024-06-21 15:53:52 -04:00 |
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Ryan Houdek
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3045578da4
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AVX128: Implement vmov{d,q}
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2024-06-21 15:53:52 -04:00 |
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Ryan Houdek
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9566dda73e
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AVX128: Implement support for vcmps{s,d}
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2024-06-21 15:53:52 -04:00 |
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Ryan Houdek
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a0ced2b685
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AVX128: Implement support for vcmpp{s,d}
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2024-06-21 15:50:26 -04:00 |
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Ryan Houdek
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df232f567b
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AVX128: Implement support for v{add,sub,mul,fmin,fmax,fdiv,sqrt,rsqrt,rcp}s{s,d}
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2024-06-21 15:50:05 -04:00 |
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Ryan Houdek
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2a6d6a9d13
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AVX128: Implement support for v{u,}comis{s,d}
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2024-06-21 15:50:05 -04:00 |
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Alyssa Rosenzweig
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cd03932bd1
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OpcodeDispatcher: tweak InsertScalarFCMPOpImpl signature
so AVX128 can reuse it.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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2024-06-21 15:50:05 -04:00 |
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Ryan Houdek
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fac9972bad
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Merge pull request #3741 from alyssarosenzweig/cleanup/comiss
OpcodeDispatcher: refactor Comiss helper
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2024-06-21 11:43:05 -07:00 |
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Alyssa Rosenzweig
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9ecb960f3a
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OpcodeDispatcher: refactor Comiss helper
AVX128 will use this, it's not SSE-specific.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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2024-06-21 14:23:20 -04:00 |
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Ryan Houdek
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424218e327
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AVX128: Implement support for vpsign{b,w,d}
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2024-06-21 08:11:22 -07:00 |
|