Ryan Houdek
9d8b60af5c
Work on x86 JIT ASM dispatcher
2020-03-06 07:56:05 +02:00
Ryan Houdek
96b0214bc1
Add new atomic ops to the AArch64 JIT
2020-03-06 07:56:05 +02:00
Ryan Houdek
e1d2a934e2
Fixes the scalar SSE ops and MOVD
2020-03-06 07:56:05 +02:00
Ryan Houdek
6fb2d1aa1f
Implements XADD x86 instruction
2020-03-06 07:56:05 +02:00
Ryan Houdek
931df90a4e
Fixes FINDMSB IR op in the x86 JIT
2020-03-06 07:56:05 +02:00
Ryan Houdek
1b58aa61f7
Implements new atomic ops in the x86 JIT
2020-03-06 07:56:05 +02:00
Ryan Houdek
6544570264
Implements VUSHR IR op in x86 JIT
2020-03-06 07:56:04 +02:00
Ryan Houdek
a684bc1aff
Implements SplatVector2/4 in x86 JIT
2020-03-06 07:56:04 +02:00
Ryan Houdek
2858adc0d3
Fixes MOVSD x86 instruction
2020-03-06 07:56:04 +02:00
Ryan Houdek
28142703ee
Fixes BTR/BTS op when destination is GPR
2020-03-06 07:56:04 +02:00
Ryan Houdek
77e7a453d3
Adds BTC x86 instruction
2020-03-06 07:56:04 +02:00
Scott Mansell
0d782bd515
Fix handling of 8/16bit loads in x64 jit.
...
Need to sign extend, otherwise junk from upper bits
can mess things up.
2020-03-06 07:56:03 +02:00
Scott Mansell
5429721350
Also make MOVXS accept the 66 prefix
2020-03-06 07:56:03 +02:00
Scott Mansell
7ec68ce815
Fix decoding legacy 66 0F XX insturctions.
2020-03-06 07:56:03 +02:00
Ryan Houdek
e2b30d9c02
Adds REV IR op to x86 JIT and AArch64 JIT
2020-03-06 07:56:03 +02:00
Ryan Houdek
255138dcc4
Adds a bunch of new instructions to the OpcodeDispatcher
2020-03-06 07:56:03 +02:00
Ryan Houdek
962669cd17
Adds new IR ops to the LLVM JIT
2020-03-06 07:56:03 +02:00
Ryan Houdek
29b7ddb67f
Adds new IR ops to the x86-64 JIT
2020-03-06 07:56:03 +02:00
Ryan Houdek
fc0ce3d1dc
Adds new IR ops to the AArch64 JIT
2020-03-06 07:56:02 +02:00
Ryan Houdek
e9d1ec6aff
Adds new IR ops to the interpreter
2020-03-06 07:56:02 +02:00
Ryan Houdek
6b636c3c26
Fixes a couple of instructions in the x86Tables
2020-03-06 07:56:02 +02:00
Ryan Houdek
2f5e2ea066
Fixes LODS and SCAS x86Table flags
2020-03-06 07:56:02 +02:00
Ryan Houdek
3bb9197e6a
Adds VAND IR Op
2020-03-06 07:56:02 +02:00
Ryan Houdek
a858296ecd
Removes SSE41, SSE42, and AVX support from CPUID
2020-03-06 07:56:01 +02:00
Scott Mansell
2babc1292c
GdbServer: Breakpoint intergation
2020-03-06 07:56:01 +02:00
Scott Mansell
9a89741ff2
gdbServer: Allow continuing
2020-03-06 07:56:01 +02:00
Scott Mansell
e050eace1d
Refactor context start/pause/step interface
2020-03-06 07:56:01 +02:00
Scott Mansell
545b542f9b
GdbServer: Implement xml target for register order
...
We can now simply memcpy much of memory state.
2020-03-06 07:56:01 +02:00
Scott Mansell
e44b3ca495
Gdbserver: Implement enough to reach gdb prompt
...
Memory is implemented, but without any checking or
invalidation.
Registers just hardcode a RIP for my test elf.
But GDB can read the elf over tcp, initilize and allow you to create breakpoints, which get
writen back before continue (which is not hooked up)
2020-03-06 07:56:01 +02:00
Scott Mansell
17ffe5a7b2
GdbServer: Support a few more packets
2020-03-06 07:56:01 +02:00
Scott Mansell
23db0f66ec
Add a skeleton of a GdbServer
2020-03-06 07:56:01 +02:00
Ryan Houdek
e0e708a9c0
Fixes three instructions necessary for shared apps to run
...
Fixes MOVHPD which was failing.
Fixes FXSTOR and FXSAVE which was accidently loading the memory location
rather than doing an LEA of the address.
2020-03-06 07:56:01 +02:00
Ryan Houdek
e9be5430b9
Adds a couple new IR ops for easy movement of registers between classes.
2020-03-06 07:56:01 +02:00
Ryan Houdek
af5a562508
Fixes bug in STOS and CMPS
...
We were storing one too many elements. So even if the counter register
was zero it would do a store or comparison
2020-03-06 07:56:00 +02:00
Scott Mansell
8a6efad301
Stub FNSTCW/FLDCW so libc.so.6 can be loaded
...
Apparently doesn't need any other x86 instructions.
Or anything more than noped out state save/restore.
2020-03-06 07:56:00 +02:00
Ryan Houdek
3f06f3e87d
Fixes bug in PUSH op with RSP source.
...
We were modifying RSP to adjust the stack first.
Then if the source used RSP then it was offset by the store size.
`push [rsp]` was broken before this
2020-03-06 07:56:00 +02:00
Ryan Houdek
2df55d303a
Fixes bug in SHR op
...
Smaller ops could have been shifting data from the larger source in to
the smaller op space when it should have been zero'd
2020-03-06 07:55:59 +02:00
Ryan Houdek
7a4d0fbfd3
Fixes bug in 64bit def mod instructions that are in 16bit mode
...
These would have been forced to 64bit when they would have wanted to be
operating in 16bit mode.
Fixes that.
2020-03-06 07:55:59 +02:00
Ryan Houdek
afdbd9ebdc
Fixes issues with PSLLDQ and PSRLDQ
...
These are whole vector shift instructions and they shift by bytes rather
than bits.
You only get an immediate offset for the instruction.
Implements two new IR ops to account for these instructions
This also doesn't match AArch64 behaviour 100%, requires two
instructions to emulate rather than the single one on the x86-side
2020-03-06 07:55:59 +02:00
Ryan Houdek
af6eefb495
Fixes crash in IR Interpreter that can occur with large functions
...
If the tmp space grew too large and had to resize then we would have
stale pointers.
Keep around the offset instead so we don't store invalid pointers.
2020-03-06 07:55:59 +02:00
Ryan Houdek
3568cdb03b
Adds VBITCast to IR Interpreter
2020-03-06 07:55:59 +02:00
Ryan Houdek
33ebeef246
Fixes IR Interpreter
...
Updates it to support the IR style and branching requirements.
2020-03-06 07:55:59 +02:00
Ryan Houdek
bc294164e3
Updates project to allow it to be installed
...
Installs as both a static library and a shared library
2020-03-06 07:55:59 +02:00
Ryan Houdek
939e210a68
Updates SonicUtils
...
Makes changes to match latest changes
2020-03-06 07:55:54 +02:00
Ryan Houdek
b58b5687e0
Fixes AArch64 custom ASM dispatcher
2020-03-06 07:55:46 +02:00
Ryan Houdek
6e72a365d9
Fixes for the AArch64 JIT
...
Custom dispatcher isn't fully working yet, but fixes a few other bugs.
2020-03-06 07:55:46 +02:00
Ryan Houdek
cb81d0a1af
Fixes CondJump on AArch64 JIT
2020-03-06 07:55:46 +02:00
Ryan Houdek
efdf490c3c
Adds support for ARM on the LLVM JIT
2020-03-06 07:55:46 +02:00
Scott Mansell
20fc6a489e
Fix STOS to not load SSA regs across blocks
2020-03-06 07:55:45 +02:00
Ryan Houdek
ee53b70bfe
Actually enable LLVM optimization passes in the LLVM JIT
...
We were using whatever was the LLVM default before.
2020-03-06 07:55:45 +02:00
Ryan Houdek