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Code Issues Packages Projects Releases 67 Wiki Activity
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990b70dcd6ea72da80e2c30dfa6063f7d7827d71
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91 Commits
Author SHA1 Message Date
Lioncache 990b70dcd6 OpcodeDispatcher: Use scalar rounding for scalar round instructions 2023-08-23 13:34:01 -04:00
Lioncache 393cea2e8b Arm64/ConversionOps: Correct AdvSIMD round-to-nearest Vector_FToI case 
This was previously using frinti, which uses the host rounding mode, rather
than round to nearest.
 2023-08-23 13:27:44 -04:00
Lioncache e89321dc60 Arm64/ConversionOps: Add scalar support to Vector_FToI 
This can be used for the scalar conversions instead of always using the
vector variants.
 2023-08-23 13:23:07 -04:00
Mai 0819338dbf Merge pull request #2970 from Sonicadvance1/optimize_pminmax 
Arm64: Optimize VFMin/VFMax
 2023-08-23 12:39:37 -04:00
Lioncache 3858e4124b OpcodeDispatcher: Remove redundant moves in AVX blend special cases 
Zero-extension will happen if necessary upon storing.
 2023-08-23 00:08:33 -04:00
Mai 819fe110da Merge pull request #2967 from Sonicadvance1/optimize_storeelement 
OpcodeDispatcher: Optimize MOVHP{S,D}
 2023-08-23 00:01:25 -04:00
Ryan Houdek f0b1030e54 Arm64: Optimize VFMin/VFMax 
We can be more optimal on the selects. This makes 3DNow! and SSE packed
min/max operations optimal.
 2023-08-22 20:59:11 -07:00
Ryan Houdek adfd6787c0 Merge pull request #2969 from lioncash/insert 
OpcodeDispatcher: Remove unnecessary moves from AVX inserts
 2023-08-22 20:51:55 -07:00
Ryan Houdek 0ee2579a5e OpcodeDispatcher: Optimize MOVHP{S,D} 
Loads can turn in to element Loads.
Stores can turn in to element stores.

These four instruction variants are now optimal.
 2023-08-22 20:42:24 -07:00
Ryan Houdek 6aa2cab41c IR: Implement support for vector store element 
Matches ARM64 ST1 semantics
 2023-08-22 20:42:24 -07:00
Mai bb2f7107cd Merge pull request #2963 from Sonicadvance1/optimize_loadelement 
OpcodeDispatcher: Optimize MOVLP{S,D} loads
 2023-08-22 23:41:59 -04:00
Lioncache c33f3ff8df OpcodeDispatcher: Remove unnecessary moves from AVX inserts 
We already zero-extend on stores when necessary.
 2023-08-22 23:29:40 -04:00
Ryan Houdek de239cde67 OpcodeDispatcher: Optimize MOVLP{S,D} loads 
This now uses the new load element IR operation and makes these
instructions optimal.

LRPCPC3 will introduce instructions in the future for TSO emulation to
help these operations, but that doesn't exist today.
 2023-08-22 20:15:16 -07:00
Ryan Houdek 5e57ec94cf IR: Implement support for vector load element 
Matches Arm64 LD1 semantics.
 2023-08-22 20:15:16 -07:00
Lioncache 2f5fae7677 OpcodeDispatcher: Remove unnecessary moves from AVX register shifts 
Zero-extension will occur automatically when necessary upon storing.
 2023-08-22 23:06:53 -04:00
Lioncache 8f8062eb4e OpcodeDispatcher: Remove redundant moves from AVX immediate shifts 
These zero-extensions will occur automatically when applicable.
 2023-08-22 22:50:10 -04:00
Lioncache e5f5629ffc OpcodeDispatcher: Remove unnecessary moves from AVX conversion operations 
These zero-extensions will already happen automatically if necessary.
 2023-08-22 22:20:13 -04:00
Ryan Houdek ead141fd90 Merge pull request #2962 from lioncash/variable 
OpcodeDispatcher: Remove unnecessary moves from AVXVariableShiftImpl
 2023-08-22 18:52:47 -07:00
Lioncache 2b071e282e OpcodeDispatcher: Remove unnecessary moves from AVXVariableShiftImpl 
We already zero-extend on a store if necessary.
 2023-08-22 21:20:34 -04:00
Ryan Houdek 14144523f7 Merge pull request #2961 from lioncash/minpos 
OpcodeDispatcher: Remove unnecessary move from VPHMINPOSUW
 2023-08-22 18:19:46 -07:00
Ryan Houdek 1f2c5fc6c6 Merge pull request #2960 from lioncash/index 
Arm64: Optimize SVE VInsElement
 2023-08-22 18:19:13 -07:00
Lioncache fa17d9fae9 OpcodeDispatcher: Remove unnecessary move from VPHMINPOSUW 
We already do a zero-extend if necessary in StoreResult.

This also lets us unify both the SSE and AVX handling code.
 2023-08-22 20:59:56 -04:00
Lioncache 398a70312e Arm64: Optimize SVE VInsElement 
This can be done without storing any data to memory and also
compressing the amount of instructions being used.

Thanks to @dougallj for the optimization suggestions.
 2023-08-22 20:36:29 -04:00
Ryan Houdek d3ed9766e8 X86Tables: Optimize MOVLPD stores 
Just use the full register size and store the lower bits.
 2023-08-22 17:33:34 -07:00
Ryan Houdek c795d42d21 OpcodeDispatcher: Optimize phminposuw 
I would now consider the XMM version of this to be optimal.

Thanks to @rygorous for giving the idea for how to optimize this!
 2023-08-22 16:29:06 -07:00
Ryan Houdek bbf9cb9d52 IR: Implements new VRev32 and LoadNamedVectorConstant ops 
VRev32 matches Arm64 semantics directly.
LoadNamedVectorConstant allows FEX to quickly load "named constants".
This will allow us to have specific hardcoded vector constant values
that we can load with a ldr(State)+ldr(Value) and will be more abused in
the future.
This also allows us to do a very simple optimization in the future where
we can optimize away redundant loads of these loads if they are used
multiple times in the same block. (Not implemented here).
 2023-08-22 16:29:06 -07:00
Mai 6c7933e7b1 Merge pull request #2957 from Sonicadvance1/optimize_pfnacc 
OpcodeDispatcher: Optimize PFNACC
 2023-08-22 10:10:11 -04:00
Ryan Houdek 364f084604 Merge pull request #2956 from Sonicadvance1/optimize_hsubp 
OpcodeDispatcher: Optimize hsubp
 2023-08-21 20:47:50 -07:00
Ryan Houdek ffa8f1e3dc Merge pull request #2955 from lioncash/sign 
OpcodeDispatcher: Remove redundant move from VPSIGN
 2023-08-21 20:47:41 -07:00
Ryan Houdek ad6738939b OpcodeDispatcher: Optimize PFNACC 
Turns out this can be even more optimal.
 2023-08-21 20:38:18 -07:00
Ryan Houdek dcb3e4ee86 OpcodeDispatcher: Optimize hsubp 
This makes the SSE version optimal.
This dramatically improves the AVX version as well.
 2023-08-21 20:22:14 -07:00
Lioncache dbbe6288de OpcodeDispatcher: Remove redundant move from VPSIGN 
StoreResult will already zero-extend if the vector is 128-bit.
 2023-08-21 23:11:07 -04:00
Ryan Houdek 1563398d2c OpcodeDispatcher: Optimize pmuludq 
MMX version was already optimal, SSE version is now also.
AVX version is significantly improved.
 2023-08-21 20:07:35 -07:00
Lioncache 920a0fb132 OpcodeDispatcher: Remove redundant move in AVXVectorScalarALUOpImpl 
Our store will already zero-extend if the vector is 128-bit.
 2023-08-21 22:39:07 -04:00
Lioncache ce8169794f OpcodeDispatcher: Remove redundant moves in AVXVectorALUOp 
We already zero-extend on a store if we have 256-bit vectors and the stored
vector is 128-bit.
 2023-08-21 22:13:29 -04:00
Mai 185e3bfcb6 Merge pull request #2950 from Sonicadvance1/optimize_pmaddwd 
OpcodeDispatcher: Optimize pmaddwd
 2023-08-21 21:39:30 -04:00
Mai 3c49b3238a Merge pull request #2949 from Sonicadvance1/optimize_phsub 
OpcodeDispatcher: Optimize phsub
 2023-08-21 21:39:02 -04:00
Ryan Houdek 2d7a3a578e Merge pull request #2931 from Sonicadvance1/optimize_psign 
Optimize PSIGN and VBSL
 2023-08-21 18:30:55 -07:00
Ryan Houdek 3a2a576c35 Merge pull request #2951 from lioncash/shift 
OpcodeDispatcher: Handle zero immediate shifts better
 2023-08-21 18:20:18 -07:00
Ryan Houdek 869136b907 OpcodeDispatcher: Optimize pmaddwd 
This is actually fairly trivial looking at it.
 2023-08-21 17:53:32 -07:00
Lioncache af8b6766d8 OpcodeDispatcher: Handle zero immediate shifts better 
In the SSE and lower cases, we don't need to do anything,
since the value is already in the destination.
 2023-08-21 20:46:41 -04:00
Ryan Houdek 30e9beba51 JIT64: Fixes i32v2 unzips 
This has just been broken since it was implemented. Turns out we had
never used these with XMM operations before today.
 2023-08-21 17:38:24 -07:00
Ryan Houdek a29076244f OpcodeDispatcher: Optimizes mpsadbw 
Two optimizations here:
1) The final VInsElement was generating three instructions
   - This itself could have been change to vzip, which would have
     removed two instructions.
2) Optimize how the pairwise elements are calculated to shave one
   instruction off the calculation.
   - addp odd elements and even elemnts first
   - Then transpose those elements
   - Then use one final addp to generate the result in the correct
     order.

The ext+uabdl+addp pairs of operations could be reordered to shave off
one temporary register usage if we really care later.
 2023-08-21 16:56:41 -07:00
Ryan Houdek 445c43792b OpcodeDispatcher: Optimize phsub 
This was...surprisingly bad. I blame myself entirely.
 2023-08-21 16:54:35 -07:00
Ryan Houdek b35f4df798 OpcodeDispatcher: Optimize SSE pmaddubsw 
Can be slightly more optimal with a slightly change algorithm but will
require implementing some IR ops which can be put off. It's only about
an instruction savings.
 2023-08-21 16:21:01 -07:00
Lioncache f1d020ce95 Interpreter: Tie SSA data elements to supported vector width 
Now, if we ever increase our vector sizes, the allocated data elements
will follow suit without needing to remember to handle this as well.
 2023-08-21 14:41:00 -04:00
Lioncache a9a7cbce21 Interpreter: Use alias for temporary vector data 
Lets us extract the size into one location for easy size
changes in the future if necessary.
 2023-08-21 14:12:55 -04:00
Ryan Houdek a3bf952f2b IR: Implements support for wide scalar shifts 
This matches x86 vector shift behaviour closely for ps{rl,ra,ll}{w,d,q}
where the vector is shifted by a scalar value that is 64-bits wide.
Anything larger than the element size will set that element to zero.

With SVE we have some new wide element shifts that match this behaviour
exactly (except supports wide shift sources rather than scalar).

This is a significant improvement even on platforms that only support
128-bit SVE.
 2023-08-20 19:16:40 -07:00
Ryan Houdek ac77986c44 IR: Implements support for saturating/rounding vector shifts 2023-08-20 13:38:23 -07:00
Ryan Houdek c5f5a03c68 OpcodeDispatcher: Optimize PSIGN 
This dramatically improves the performance of the PSIGN instructions.
 2023-08-20 13:38:23 -07:00