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Code Issues Packages Projects Releases 67 Wiki Activity
247 Commits 11 Branches 71 Tags
9870547d503aed7b0a1ced036dbc251c55673fd9
Commit Graph
152 Commits
Author SHA1 Message Date
Ryan Houdek 9870547d50 Fixes 32bit element selection for SHUFP 2020-03-06 07:56:18 +02:00
Ryan Houdek f645bd7901 Adds a few new IR ops 
Fixes REP CMPS. It needs to also break when ZF == 0
Fixes REPNE SCAS. It shouldn't set ZF to 0 on entry. Could result in erroneous flag setting.
Implements a few new x86 ops
 2020-03-06 07:56:18 +02:00
Ryan Houdek 75f7bc0abd Fixes FindMSB op for the interpreter for 8bit/16bit types 
Was zexting to 32bit and thing doing a findMSB which was wrong
 2020-03-06 07:56:17 +02:00
Ryan Houdek ec5f3a6854 Fixes LEA instruction 
LEA changes behaviour based on the ordering of the prefixes on the
instruction

eg:
66 48 8d 3d ffffffff: lea rdi, [rip - 1]
48 66 8d 3d ffffffff: lea di, [rip - 1]

So we need to know the order of a few of the prefixes.
In the future this should probably be switched to a three deep stack to
have the ordering but for now this'll do
 2020-03-06 07:56:17 +02:00
Ryan Houdek 64e863a5a0 Adds a few more instructions to the OpcodeDispatcher 2020-03-06 07:56:17 +02:00
Ryan Houdek e854112927 Implements Unified memory in the x86 JIT 2020-03-06 07:56:17 +02:00
Ryan Houdek c336a09641 Adds new IR ops to interpreter and x86 JIT 2020-03-06 07:56:17 +02:00
Ryan Houdek fe170846f4 Fixes LEA X86Table flag 
Default operating size was wrong
 2020-03-06 07:56:17 +02:00
Ryan Houdek ae2689d9e2 Fleshes out a couple x87 instruction table ops 2020-03-06 07:56:17 +02:00
Ryan Houdek 0dcd4bc0b3 Removes some CPUID feature flags 
We don't support AVX512, XOP, or FMA4
 2020-03-06 07:56:17 +02:00
Ryan Houdek 8d293e9184 Adds support for unified memory to the interpreter core 2020-03-06 07:56:17 +02:00
Ryan Houdek a79197bd39 Supports unified memory in the Core 2020-03-06 07:56:17 +02:00
Ryan Houdek d5402bce2b Lets the block cache understand the unified address space option 
There is a limitation that all executable code must live above the
memory base at this moment
 2020-03-06 07:56:16 +02:00
Ryan Houdek c7c5d8bdd7 Cleanup the CPUID interface 
I saw LLVM using CPUID function 0x14 so I decided to fill out the map
with the basic leafs
 2020-03-06 07:56:16 +02:00
Ryan Houdek ccd7a18445 Fixes a few SSE instruction flags 2020-03-06 07:56:16 +02:00
Ryan Houdek 669aa99d3e Fixes stale data bug in the interpreter 2020-03-06 07:56:16 +02:00
Ryan Houdek d8b3e3bd84 Adds Popcount x86 instruction to dispatcher 2020-03-06 07:56:16 +02:00
Ryan Houdek ed12a8a242 Fixes x86 instruction decoding. 
In the case of modrm + immediate then the immediate would end up
overwriting Src1 due to the the order of the decoding.
Changes Src1 and Src2 to an array and use a variable to index the array.
Causes a bit of code churn but fixes instruction decoding and allows
easier expansion in the future for instructions that have more sources
like AVX
 2020-03-06 07:56:15 +02:00
Ryan Houdek 9135661861 Fixes edge case when instruction declares 66h and REX.W 
REX.W takes precedence over 66h
 2020-03-06 07:56:15 +02:00
Ryan Houdek bdda36496b Implements FindTrailingZeros IROp in the interpreter 2020-03-06 07:56:15 +02:00
Ryan Houdek 8a2bf00fb6 Enforces register classes on loadstores 
Register class for loadstores must be declared upfront.
This was causing a pain point when we were trying to load <16byte in to
FPRs, which was requiring a GPR<->FPR dance.
 2020-03-06 07:56:15 +02:00
Ryan Houdek 472ec5f5cf Adds 11 new emulated syscalls 2020-03-06 07:56:15 +02:00
Ryan Houdek d2bfb39b54 Disable RDRand in CPUID 2020-03-06 07:56:15 +02:00
Ryan Houdek 7ade645af2 Adds vector compare ops to OpDispatcher 2020-03-06 07:56:14 +02:00
Ryan Houdek 39802cc464 Adds a couple nop implementation of ops in OpDispatcher 2020-03-06 07:56:14 +02:00
Ryan Houdek 67ac4f015f Adds ANDN to OpDispatcher 2020-03-06 07:56:14 +02:00
Ryan Houdek 1f4418b463 Adds missing move to OpDispatcher 2020-03-06 07:56:14 +02:00
Ryan Houdek 134fa50f8b Adds fsqrt and frsqrt to OpDispatcher 2020-03-06 07:56:14 +02:00
Ryan Houdek e260378736 Fix a couple x86 instruction definitions 2020-03-06 07:56:14 +02:00
Ryan Houdek dacd20f44b Fixes interpreter temp allocation size 2020-03-06 07:56:14 +02:00
Ryan Houdek 9bc899aba0 Changes CMPS to not break RA 
RA isn't happy with how this is arranged, so it needs to be changed
until RA is good enough to support it
 2020-03-06 07:56:14 +02:00
Ryan Houdek c39f23802c Fixes ULE Select on x86 JIT 2020-03-06 07:56:14 +02:00
Ryan Houdek 9b19d23977 Fixes FindMSB in Interpreter and Arm64 JIT 2020-03-06 07:56:14 +02:00
Ryan Houdek 2889c860d4 Adds new vector IR ops 2020-03-06 07:56:14 +02:00
Ryan Houdek a8d7549b13 Fixes CPUID call in Arm64 JIT 2020-03-06 07:56:13 +02:00
Ryan Houdek 69d6c09436 Fixes AArch64 JIT compiling 2020-03-06 07:56:13 +02:00
Ryan Houdek 07faaaa0fd Make sure to not do pops at function end if from within custom dispatch for x86 2020-03-06 07:56:13 +02:00
Ryan Houdek 92e4be828f Implements new RA pass that supports PHI nodes 
Has a heuristic that changes from a map lookup and a linear scan
depending on the number of SSA values. Map lookup is faster for larger
blocks while for smaller blocks linear scan is faster.

Block scan is 1.5x - 2x faster for a 30k SSA value block I was looking
at.
 2020-03-06 07:56:13 +02:00
Ryan Houdek d5cb87d1eb Adds Phi helper functions to OpDispatcher 2020-03-06 07:56:08 +02:00
Scott Mansell 26141e426a Fix unsigned/signed compare conditions 
Also, rename to match the LLVM naming style, which is less confusing.
 2020-03-06 07:56:07 +02:00
Ryan Houdek fb17e4d440 Adds atomic ops to the Interpreter 2020-03-06 07:56:07 +02:00
Scott Mansell 7f840aa3e9 Basic FADD implementation 
Only handles addition of two positive numbers
 2020-03-06 07:56:07 +02:00
Ryan Houdek 3d0c11c770 Fixes VSLI and VSRI on AArch64 
I misunderstood these instructions on the AArch64 side.
VSLI/VSRI doesn't operate on 128bit wide vectors. Its scalar version
only works on 64bit.
We have to move the vector to GPRs and do some bit twiddling then move
the full 128bit vector back after the fact
 2020-03-06 07:56:07 +02:00
Ryan Houdek e3bbb8a580 Fixes a couple AArch64 JIT Atomic Fetches 
Swap wasn't storing in to destinationo
And and Sub weren't using the right registers
 2020-03-06 07:56:07 +02:00
Ryan Houdek 520d098e23 Implements VCastFromGPR in AArch64 JIT 2020-03-06 07:56:07 +02:00
Scott Mansell f5bf8eaeb2 Add FST/FSTP m80 2020-03-06 07:56:07 +02:00
Scott Mansell bbd951603f Add FLD m32/m64 
Currently produces incorrect results on infinities/denormals.
 2020-03-06 07:56:06 +02:00
Scott Mansell 1dee7cb037 Append x87 flags to cpustate flags[] 2020-03-06 07:56:06 +02:00
Scott Mansell 4fe10ca130 Add Load/StoreContextIndexted IR instructions 
Useful for things like x87 where instructions can dynamically index
into a resgister file.

This commit includes support for irint and x86 jit.
 2020-03-06 07:56:06 +02:00
Scott Mansell bb879a7beb Fix FLD instruction flags 2020-03-06 07:56:06 +02:00