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6993f4fd8dbe73b78050be201c5cb7ea529b437d
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768 Commits
Author SHA1 Message Date
Mai 6993f4fd8d Merge pull request #3400 from Sonicadvance1/revert_runtime_longmode_switch 
Revert #3303
 2024-02-02 11:53:44 -05:00
Paulo Matos 4623544f69 Improve XCHG operations 
Marking loads as allowing upper garbage simplifies some operations.
Update InstCountCI as well.
 2024-02-02 08:16:13 +00:00
Ryan Houdek ccf1402fe6 Revert "FEXCore: Accurately store segment descriptors" 
This reverts commit 8648fb1485.
 2024-02-01 18:14:30 -08:00
Ryan Houdek da0e1b515a Revert "OpcodeDispatcher: Initial support for runtime long-mode switch" 
This reverts commit 9e5d7aa5fe.
 2024-02-01 18:14:24 -08:00
Ryan Houdek cec1814a09 Merge pull request #3384 from pmatos/CDQOp-Opt 
Optimize CDQOp
 2024-01-31 17:51:23 -08:00
Mai 4d49ac7c3d Merge pull request #3387 from alyssarosenzweig/opt/rotates 
Optimize rotates
 2024-01-31 18:20:40 -05:00
Alyssa Rosenzweig 6d13d9fb56 Merge pull request #3395 from pmatos/StaticAnalysis 
Code cleanup - mainly dead store removal; NFC
 2024-01-31 17:24:48 -04:00
Mai ae7dc250db Merge pull request #3386 from alyssarosenzweig/opt/shift 
Optimize shifts a bit
 2024-01-31 14:11:58 -05:00
Paulo Matos e4560ed0c8 Code cleanup - mainly dead store removal; NFC 
scan-build found a few dead stores that can be easily cleaned-up
 2024-01-31 08:35:55 +00:00
Alyssa Rosenzweig f3eee8f305 OpcodeDispatcher: optimize bextr's length sanitize 
reordering the operations saves an immediate move.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:28:06 -04:00
Alyssa Rosenzweig f66085f4a7 OpcodeDispatcher: optimize bextr's (1 << x) - 1 
little algebraic trick I cribbed from llvm

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:28:06 -04:00
Alyssa Rosenzweig c9461d9997 OpcodeDispatcher: optimize BEXTR flag setting 
use native test.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:28:06 -04:00
Alyssa Rosenzweig d5eb99fac8 OpcodeDispatcher: optimize popcount flags 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:28:06 -04:00
Alyssa Rosenzweig f3175848b1 OpcodeDispatcher: use lzcnt flag gen for tzcnt 
as far as flags go, they're identical: set ZF for zero output, set CF for output
= DestSize, undef the rest. merge the impls, so we get the optimized lzcnt impl
for tzcnt.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:28:06 -04:00
Alyssa Rosenzweig 3dd597a591 OpcodeDispatcher: optimize lzcnt 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:28:06 -04:00
Alyssa Rosenzweig e8e05252f0 OpcodeDispatcher: optimize BLSI 
and explain why the suss thing we did before was actually right all along.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:28:06 -04:00
Alyssa Rosenzweig 93cef53ec0 OpcodeDispatcher: optimize blsr flags 
reorder to avoid nzcv clobber

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:28:06 -04:00
Alyssa Rosenzweig 3a19133267 OpcodeDispatcher: fix inverted BLSR carry 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:28:06 -04:00
Alyssa Rosenzweig 9b309b2102 OpcodeDispatcher: optimize blsmsk flags 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:28:06 -04:00
Alyssa Rosenzweig fe88b904c9 OpcodeDispatcher: fix missing SF set with blsmsk 2024-01-30 22:28:06 -04:00
Alyssa Rosenzweig 2e63c6d547 OpcodeDispatcher: fix inverted CF with blsmsk 
CF set if SRC = 0

per https://www.felixcloutier.com/x86/blsmsk

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:28:06 -04:00
Alyssa Rosenzweig 0bc9e1a409 OpcodeDispatcher: clobber OF with shift immediate 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:26:59 -04:00
Alyssa Rosenzweig 338f12845d OpcodeDispatcher: save a constant in shld 
one weird trick

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:26:59 -04:00
Alyssa Rosenzweig b3ae81f75f OpcodeDispatcher: allow garbage on shld shift 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:26:59 -04:00
Alyssa Rosenzweig c1a1c37980 OpcodeDispatcher: mark ideas to improve SHLD 
a bit tricky right now.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:26:59 -04:00
Alyssa Rosenzweig fb6f850bb4 OpcodeDispatcher: remove rcl sub 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:22:57 -04:00
Alyssa Rosenzweig b6d8749525 OpcodeDispatcher: remove select from rcl 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:22:57 -04:00
Alyssa Rosenzweig d3f1397325 OpcodeDispatcher: eliminate constants in RCR 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:22:57 -04:00
Alyssa Rosenzweig 0a164428fa OpcodeDispatcher: eliminate select in RCR 
the nzcv clobber I actually came ofr

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:22:57 -04:00
Alyssa Rosenzweig 7496175100 OpcodeDispatcher: optimize 32-bit rcl/rcr 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:22:57 -04:00
Alyssa Rosenzweig 0616a9cef1 OpcodeDispatcher: eliminate move in rcr 1-bit 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:22:57 -04:00
Alyssa Rosenzweig 97f8775354 OpcodeDispatcher: optimize <32-bit rcr op1 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:22:57 -04:00
Alyssa Rosenzweig c92099aa98 OpcodeDispatcher: fuse orlshl in rcr 1-bit 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:22:57 -04:00
Alyssa Rosenzweig 7c288b09f1 OpcodeDispatcher: rmif mask rcl smaller OF 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:22:57 -04:00
Alyssa Rosenzweig 680af7b1b0 OpcodeDispatcher: rcr op 8x1 cleanup 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:22:57 -04:00
Alyssa Rosenzweig 349bc9efab OpcodeDispatcher: unify rcr op 1bit codepaths 
get additional opt for <32-bit

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:22:57 -04:00
Alyssa Rosenzweig ad5c3cb268 OpcodeDispatcher: rmif mask for OF in rcr smaller 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:22:57 -04:00
Alyssa Rosenzweig be8d37ef3d OpcodeDispatcher: optimize 32-bit rol/ror imm 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:22:57 -04:00
Alyssa Rosenzweig 6ad2514bfe OpcodeDispatcher: rmif mask rcl smaller cf 
better on flagm. extra moves on non-flagm but, meh.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:22:57 -04:00
Alyssa Rosenzweig 3fa6129a14 OpcodeDispatcher: rmif mask rcr smaller cf 
and do some constant folding to do so more.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:22:57 -04:00
Alyssa Rosenzweig a57cebaf58 OpcodeDispatcher: skip OF calc for constant rotate >= 2 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:22:57 -04:00
Alyssa Rosenzweig 34fdb14da1 OpcodeDispatcher: add and use AndConst 
this skips the constant folding, which saves the branching in the rotate
immediate implementations.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:22:57 -04:00
Alyssa Rosenzweig 974baca09c OpcodeDispatcher: allow upper garbage with rcl/rcr smaller 
we're masking immediately to something smaller

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:22:57 -04:00
Alyssa Rosenzweig f22094a493 OpcodeDispatcher: use a branch for 8/16-bit rotate flags 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:22:57 -04:00
Alyssa Rosenzweig d979b3a1da OpcodeDispatcher: note idea to further optimize rcl 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:22:57 -04:00
Alyssa Rosenzweig 6d82c957fa OpcodeDispatcher: fuse orlshl in rcl 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-30 22:22:57 -04:00
Mai fa3352004e Merge pull request #3381 from alyssarosenzweig/opt/masking 
Allow upper garbage on a bunch of instructions
 2024-01-30 10:07:53 -05:00
Ryan Houdek ce2924731e vixl/simulator: Enlarge simulator stack size 
Simulator stack size defaults to 8KB. This new unit test requires at
least 15360 stack size. Just push it up to 8MB.
 2024-01-29 19:48:38 -08:00
Mai 31a4158957 Merge pull request #3383 from alyssarosenzweig/opt/ptest 
Optimize PTEST and VTESTP
 2024-01-29 13:30:53 -05:00
Mai 58f3d3caf5 Merge pull request #3380 from alyssarosenzweig/opt/pdep 
Optimize PDEP
 2024-01-29 13:27:15 -05:00