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116 Commits
Author SHA1 Message Date
Stefanos Kornilios Mitsis Poiitidis 5fa5e49c58 IR: Add DeadGPRStoreElimination 
This is based on the Flag Elimination pass, and is not optimal - but does eliminate quite a few dead stores.
 2020-11-05 23:57:57 +02:00
Stefanos Kornilios Mitsis Poiitidis 93e372c7a4 IR/JITs: Inline Constants Implementation 
Based on @phire's idea, Inline constants are constants that can be used as imms in instructions.

This
- Adds OP_INLINECONSTANT to represent them in the IR
- Modifies the ConstProp pass to transform OP_CONSTANT to OP_INLINECONSTANT based on per-platform heuristics
- Modifies the backends to use imms
- Supported opcodes: Add, Sub, Lsl, Lsr, Asr, Ror, Rol
 2020-10-22 18:49:17 +03:00
Ryan Houdek a8175ca891 Moves away from std::is_pod 
This is deprecated in C++20 and will spam warnings all over the place
 2020-10-17 16:02:55 -07:00
Ryan Houdek 2c2d73839b Adds new AES IR ops 2020-09-30 00:05:55 -07:00
Ryan Houdek badc7f6562 Merge pull request #434 from Sonicadvance1/pmulhrsw 
Implements SSSE3 PMULHRSW
 2020-09-27 10:38:14 -07:00
Ryan Houdek 62158d4f8c Implements new VectorImm IR op 2020-09-26 15:30:20 -07:00
Ryan Houdek 83ac23be21 Implements new VTBL1 IR op 
This perfectly matches the AArch64 variant and almost perfectly matches
x86's pshufb instruction
 2020-09-26 12:59:34 -07:00
Stefanos Kornilios Mitsis Poiitidis 83db01f505 Merge pull request #429 from Sonicadvance1/psign 
Implements support for SSSE3 PSIGN{B,W,D}
 2020-09-26 20:20:06 +03:00
Stefanos Kornilios Mitsis Poiitidis de62124b95 Merge pull request #428 from Sonicadvance1/lzcnt 
Implements ABM's LZCNT instruction
 2020-09-26 20:11:47 +03:00
Ryan Houdek c6385093eb Adds a few new IR ops 
VectorZero, useful to generate a zero vector without any previous
dependencies

and comparisons with zero which ARM supports faster versions of
 2020-09-24 19:34:19 -07:00
Ryan Houdek 479505b069 Implements new CountLeadingZeroes IR op 2020-09-23 22:13:28 -07:00
Ryan Houdek 6c37a4dea6 Adds support for BCD x87 intructions 2020-09-22 23:56:03 -07:00
Stefanos Kornilios Mitsis Poiitidis 91bea781f4 Merge pull request #408 from Sonicadvance1/rounding_mode_host 
Adds new IR ops for supporting host rounding mode conversion
 2020-09-23 09:50:37 +03:00
Ryan Houdek e4182108f6 Adds new IR ops for supporting host rounding mode conversion 2020-09-22 18:42:23 -07:00
Ryan Houdek adb9b111ca Fixes crash when SSA value has size of zero 
In the case of an invalid SSA destination size, the IR validation pass
would catch it and then when printing the IR it would crash with a
divide by zero.
Fixes that.
 2020-09-22 18:20:32 -07:00
Ryan Houdek 00f0047cff Merge pull request #391 from phire/Remove_BFE 
Remove unneeded BFEs around flag generation code.
 2020-09-16 22:27:59 -07:00
Scott Mansell 5048753e37 Undo limitation of ASHR to 32/64bit 
This should really be done later in a sperate PR.

 1. We don't have proper unit test coverage
 2. I still didn't get this right at time of removal
 3. I haven't done the jit changes to go along with this.
 2020-09-17 16:26:41 +12:00
Scott Mansell 96603495ec OpcodeDispatcher: Remove BFEs from flag-gen calls 2020-09-17 14:59:50 +12:00
Scott Mansell d4844703d9 ReplaceAllUses: Early exit optimization 2020-09-17 11:29:57 +12:00
Scott Mansell b0cfc19267 Fast replacement path for constants 2020-09-17 11:29:57 +12:00
Ryan Houdek d424cf0eee Merge pull request #365 from phire/IR_iterators 
Refactor the IR Interface to prevent "foot-shooting"
 2020-09-16 11:24:44 -07:00
Ryan Houdek addcb824e2 Merge pull request #390 from FEX-Emu/skmp/add-pendatic-smc 
SMC: Add --smc-full-checks, implement frontend, irint, irjit, unit test
 2020-09-16 09:26:35 -07:00
Stefanos Kornilios Mitsis Poiitidis df3bdf361f SMC: Add --smc-full-checks, implement frontend, irint, irjit, unit test 2020-09-16 01:15:21 +03:00
Ryan Houdek 8878278402 Implements new EXTR IR op 
This maps directly to AArch64's EXTR op.
Maps closely to x86's SHRD instruction
 2020-09-13 17:28:09 -07:00
Ryan Houdek e9b74b0230 Initial Callback support 
This interface is for native host code to be able to call back in to JIT
to execute guest code.
This is mainly for thunks but could be used for other purposes.
This can cross a couple ABI boundaries so one must be careful when
calling in to this
 2020-09-11 15:48:51 -07:00
Scott Mansell 3102fb78e7 Minor IR validation fixes 2020-09-11 21:50:30 +12:00
Scott Mansell 92a64aad2e Update DeadFlagStoreElimiateion pass 2020-09-11 21:50:30 +12:00
Scott Mansell 0a78651cce Fix ListBegin usages that got missed. 
There are still a few in interpeter and IR compaction
which are harder to fix.
 2020-09-11 21:50:30 +12:00
Scott Mansell 70b3456536 Swich register allocator to new scheme. 2020-09-11 21:50:30 +12:00
Scott Mansell e756b46189 Allow AllNodes to iterate in reverse 
We replace Dummy with the old unused BeginBlock
and pointing it at block header like EndBlock
 2020-09-11 21:50:30 +12:00
Scott Mansell 3c6dbd0ade Change iterator type of IR.at 
And switch over more passes to use the new interfaces.
 2020-09-11 21:50:30 +12:00
Scott Mansell 6b26290b42 Switch most passes to use the new interface. 2020-09-11 21:50:27 +12:00
Scott Mansell df6618a4d2 New replace node functions 
Probally doesn't build
 2020-09-11 21:48:03 +12:00
Scott Mansell 36afd5b1c6 Block Iterator: Use structured bindings 2020-09-11 21:48:03 +12:00
Scott Mansell 446b261f24 Iterator for blocks 2020-09-11 21:48:03 +12:00
Scott Mansell 316a2f8d96 IRValidation: Add arg liveness, numUses checks 2020-09-11 21:48:03 +12:00
Ryan Houdek 07cb2c5ca2 Merge pull request #337 from FEX-Emu/skmp/dead-flags-mb 
IR: Add DeadFlagStoreElimination
 2020-09-10 16:43:52 -07:00
Stefanos Kornilios Mitsis Poiitidis 0adb874755 IR/ConstProp: Disable BFE identity as it breaks cs:go 2020-09-07 00:58:29 +03:00
Stefanos Kornilios Mitsis Poiitidis 3083f9e12e Merge pull request #332 from FEX-Emu/skmp/iterative-rclse 
IR: Iterative RCLSE
 2020-09-03 05:18:11 +03:00
Stefanos Kornilios Mitsis Poiitidis 2fb68583a0 IR: Add DeadFlagStoreElimination 
Mutlblock pass that eliminates flag stores that are never read.

This is a sibling to RCLSE and will likely be absorbed by it when we add MB support there.
 2020-09-02 21:57:39 +03:00
Stefanos Kornilios Mitsis Poiitidis b9ed084cc5 IR: Add identity opts for AND/OR/XOR 2020-09-02 21:50:54 +03:00
Stefanos Kornilios Mitsis Poiitidis aa3dc52799 RCLSE: Iterate until there are no changes 2020-09-02 21:34:39 +03:00
Ryan Houdek 74a310eeb2 Enables assertions option from cmake 2020-08-29 23:35:26 -07:00
Scott Mansell 65af0335dd DCSE: Refactor LoadContext slightly 
* Use a single path for both truncated and non-truncated reads
  * Support more truncation types
  * Support truncating partial reads
 2020-08-26 00:47:40 +12:00
Scott Mansell 5cb0827ec0 DCSE: Optimise partial reads. 2020-08-26 00:47:40 +12:00
Scott Mansell 5119a0bdb3 Elimiante ALU IR nodes that don't zero extend 
Add and substract were the main culprits here.

We are trying to more towards a state where:
  * Every IR op can expect it isn't given extra bits
     on it's input
  * Every IR op never sets more bits than it's size
  * All unnessicary BFEs are never emitted
  * ARM doesn't have to implement special 8 and 16bit versions of IR ops
      All masking required to implement 8/16bit math on
      arm should be explictly generated from Opcode decoder
 2020-08-26 00:47:40 +12:00
Scott Mansell 9af289eb9c Fix Truncation on context load elimitation 2020-08-26 00:47:40 +12:00
Scott Mansell 66aa9d1953 Formalise that store* ops should zext/truncate 
The IR mostly worked this way already.
The one change I needed to make was in DCSE.

DCSE needs to add an explict truncate whenever an eliminated store was
doing an implict trunctate.
 2020-08-26 00:47:01 +12:00
Scott Mansell 3989772a4f Remove OP_Zext 
Zext has confusing sematics and does excatly the same thing as BFE

 * Repace with other ops (mostly BFE)
 * Allow specifying BFE size
 2020-08-26 00:47:01 +12:00
Ryan Houdek b38983df35 Implements new TSO loadstore IR ops. 
These need to end up being specially handled on non-x86 platforms
 2020-08-12 15:24:00 -07:00