Alyssa Rosenzweig
58a3d174ec
OpcodeDispatcher: explain why we provide defined bsf behaviour
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-10-22 13:36:24 -04:00
Alyssa Rosenzweig
9c605e7333
OpcodeDispatcher: optimize bsf/bsr
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-10-22 13:31:49 -04:00
Alyssa Rosenzweig
1fd7e88ffd
OpcodeDispatcher: optimize cmp in cmpxchg
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-10-22 13:29:47 -04:00
Alyssa Rosenzweig
c5e7da0631
OpcodeDispatcher: optimize more cmpxchg mask
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none of it matters.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-10-22 13:29:47 -04:00
Alyssa Rosenzweig
68f58e415f
OpcodeDispatcher: optimize cmpxchg masking
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-10-22 13:29:47 -04:00
Paulo Matos
10ec6b63b6
Fix FXTRACT for 0.0 and -0.0
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Fixes fxtract by returning the correct values for 0.0 and -0.0. We moved the split of fxtract into _sig and _exp, to the opcode dispatcher, to ease some comparisons.
Also removed the IR node F80XTRACTStack which is not needed anymore.
2024-10-17 09:05:10 +02:00
Paulo Matos
0d53f2b45c
Implements explicit state switch between X87 and MMX
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Fixes #3850
2024-10-15 17:58:53 +02:00
Alyssa Rosenzweig
e2d58809ed
OpcodeDispatcher: rm dead
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-10-02 13:38:48 -04:00
Alyssa Rosenzweig
967a74cda9
OpcodeDispatcher: manually inline constants
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less work for constprop.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-10-02 13:38:48 -04:00
Ryan Houdek
dc2a26582f
FEXCore/OpcodeDispatcher: Fixes missing static on some tables
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This was causing egregious stack usage in these two functions
2024-09-16 18:52:55 -07:00
Ryan Houdek
c984bdb42a
OpcodeDispatcher: Remove previous template instantiantions and use Bind
2024-09-16 18:52:54 -07:00
Ryan Houdek
2645b374a7
OpcodeDispatcher: Deduplicate InstallToTable helper
2024-09-16 18:52:54 -07:00
Ryan Houdek
0e57cbf5b9
OpcodeDispatcher: Remove EVEX table install
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This hasn't been necessary for quite a while as we handle
invalid/unsupported opcodes in the frontend now.
2024-09-16 17:40:20 -07:00
Ryan Houdek
c7413d96ad
OpcodeDispatcher: Constexpr-ify VEX & VEXGroup tables
2024-09-16 17:40:20 -07:00
Ryan Houdek
f3ba8cb33c
OpcodeDispatcher: Constexpr-ify DDD tables
2024-09-16 17:40:20 -07:00
Ryan Houdek
e714933b10
OpcodeDispatcher: Constexpr-ify H0F3A tables
2024-09-16 17:40:20 -07:00
Ryan Houdek
9a0f83cbf6
OpcodeDispatcher: Constexpr-ify H0F38 tables
2024-09-16 17:40:20 -07:00
Ryan Houdek
c4d30e8437
OpcodeDispatcher: Constexpr-ify SecondaryModRM tables
2024-09-16 17:40:20 -07:00
Ryan Houdek
7b30df8a56
OpcodeDispatcher: Constexpr-ify SecondaryGroup tables
2024-09-16 17:40:20 -07:00
Ryan Houdek
86aa459dd1
OpcodeDispatcher: Constexpr-ify PrimaryGroup tables
2024-09-16 17:40:20 -07:00
Ryan Houdek
6c9a47fc71
OpcodeDispatcher: Constexpr-ify Secondary OpSizeMod tables
2024-09-16 17:40:20 -07:00
Ryan Houdek
7a72cf631b
OpcodeDispatcher: Constexpr-ify Secondary RepNEMod tables
2024-09-16 17:40:20 -07:00
Ryan Houdek
3d98eef7b8
OpcodeDispatcher: Constexpr-ify Secondary RepMod tables
2024-09-16 17:40:20 -07:00
Ryan Houdek
f2011b0b79
OpcodeDispatcher: Constexpr-ify Secondary base tables
2024-09-16 17:40:19 -07:00
Ryan Houdek
37a70e2ec6
FEXCore: Convert Base tables over to constexpr
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Only doing the single table for review purposes. Once reviewed I will
hammer out the remaining tables.
Similar to #3320 , most of the OpcodeDispatcher tables can be consteval
and made to be a compile time constant. This just requires shuffling the
code slightly. The idea is to get almost all of the table setup out of
the `InstallOpcodeHandlers` function and instead only install the
handlers that change based on 32-bit or 64-bit, just like the x86 tables
we also did.
2024-09-13 11:39:09 -07:00
Ryan Houdek
a94aaca0ec
OpcodeDispatcher: Add default FEX_UNREACHABLE
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This can't happen but if it changes then make sure we capture it.
2024-09-08 18:03:20 -07:00
Alyssa Rosenzweig
e9ab514962
IR: push parity evaluation down
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so we can optimize it globally
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-09-07 08:26:04 -04:00
Billy Laws
f7b911ca43
OpcodeDispatcher: Do not forbid INT 2E syscalls on 64-bit Windows
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This works fine on real Windows and is relied on by wine as SystemCall
is set to 1 in KUSER_SHARED_DATA, which causes the ntdll thunks to use
it over `syscall`
2024-09-06 15:58:17 +00:00
Ryan Houdek
fd4f6b8020
FEXCore: Dynamically scale TSC
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When I implemented TSC scaling originally, I chose a scale factor of 128
because it basically covered the range of devices we cared about without
going too high. I also only tested devices that had a TSC scale factor
from 19.2Mhz to 34Mhz. Turns out there is hardware that also has a 48Mhz
cycle counter, which cause them to effectively have a 6.1Ghz cycle
counter, which is kind of absurd.
Instead of a fixed scale, just calculate the amount of scaling we need
to get >= the minimum threshold of 1Ghz. This will change the shift from
7 to 5 or 6 for the faster cycle counter devices.
Of course if someone wants to know the scale factor they can still use
cpuid function 15h to know it.
Fixes #4026
2024-09-03 13:41:31 -07:00
Alyssa Rosenzweig
335cd9180e
OpcodeDispatcher: optimize mul rax
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-08-27 12:32:43 -04:00
Mai
2829ad56a1
Merge pull request #3996 from Sonicadvance1/more_bind
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OpcodeDispatcher: Convert more template handlers to Bind handlers
2024-08-23 18:27:59 -04:00
Billy Laws
ef823ce82b
OpcodeDispatcher: Allow x86 code to read CNTVCT on ARM64EC
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Required by newer insider preview versions, I noticed many crashes with
this exception number and QueryPeformanceCounter in the backtrace,
testing with XTA found it to not be passed through and instead write
the host CNTVCT (unscaled) into RAX. No other registers seem to be
affected.
2024-08-23 21:46:11 +00:00
Ryan Houdek
1d00ad6030
OpcodeDispatcher: Convert VectorVariableBlend to Bind handler
2024-08-22 15:09:44 -07:00
Ryan Houdek
23a076c313
OpcodeDispatcher: Convert packed vector shifts to Bind handler
2024-08-22 15:07:09 -07:00
Ryan Houdek
57eacab654
OpcodeDispatcher: Convert VBROADCASTOp to Bind handler
2024-08-22 14:59:25 -07:00
Ryan Houdek
b4093a8888
OpcodeDispatcher: Convert packed HSub to Bind handler
2024-08-22 14:57:40 -07:00
Ryan Houdek
7c5a9b5d6a
OpcodeDispatcher: Convert AVXVectorVariableBlend to Bind handler
2024-08-22 14:55:34 -07:00
Ryan Houdek
12b3c82d83
OpcodeDispatcher: Convert PExtr to Bind handler
2024-08-22 14:54:26 -07:00
Ryan Houdek
66520bce0a
OpcodeDispatcher: Convert VPACK{U,S}S to Bind handler
2024-08-22 14:52:41 -07:00
Ryan Houdek
25cc2bdcb8
OpcodeDispatcher: Convert VPERMILImm to Bind handler
2024-08-22 14:51:02 -07:00
Ryan Houdek
f98b18800c
OpcodeDispatcher: Convert MOVMSK to Bind handler
2024-08-22 14:49:57 -07:00
Ryan Houdek
0dd687a7a1
OpcodeDispatcher: Convert SHUFOp to Bind handler
2024-08-22 14:47:30 -07:00
Ryan Houdek
1aff3acbb9
OpcodeDispatcher: Convert PSHUFW to Bind handler
2024-08-22 14:45:04 -07:00
Ryan Houdek
a6ab2ca30d
OpcodeDispatcher: Convert PUNPCKH to Bind handler
2024-08-22 14:42:24 -07:00
Ryan Houdek
ca43e2a61c
OpcodeDispatcher: Convert PUNPCKL to Bind handler
2024-08-22 14:39:45 -07:00
Alyssa Rosenzweig
ce8e6e5c0c
OpcodeDispatcher: optimize adc 0
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clang generates this.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-08-22 10:51:06 -04:00
Alyssa Rosenzweig
6951284924
OpcodeDispatcher: optimize ADCX/ADOX
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rewrite to use native adcs with flag fixups.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-08-21 17:52:22 -04:00
Alyssa Rosenzweig
b03c613fbf
OpcodeDispatcher: optimize JP/JNP
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fuse and+cbnz into tbz/tbnz.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-08-21 17:52:22 -04:00
Alyssa Rosenzweig
b893bdb8df
OpcodeDispatcher: optimize fcmovu
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-08-21 17:52:22 -04:00
Alyssa Rosenzweig
db45f6eec8
OpcodeDispatcher: optimize test with small immediate
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-08-21 17:52:22 -04:00