Commit Graph
19 Commits
Author SHA1 Message Date
Ryan Houdek 559cf6491a InstCountCI: Support overriding AFP features
Also disable AFP under the vixl simulator by default since it doesn't support it.
2023-10-07 11:48:42 -07:00
Ryan Houdek 5b7ba06d5c FEXCore: Support crypto extensions in HostFeatures override
Enables in InstCountCI so Pi users can run InstCountCI can run the tests
without breaking on crypto operations.

When crypto is enabled or disabled just wholesale change AES, CRC32, and
PMULL 128-bit in one step. We don't really care about partial support
here.
2023-10-05 17:41:08 -07:00
Ryan Houdek d5a4d9b17f InstCountCI: Adds option to disable cssc for tests
One x87 instruction was using CSSC abs
2023-10-02 16:26:14 -07:00
Ryan Houdek 7141332f6f InstCountCI: Support setting environment variables in tests
This will allow us to enable FEX options through environment variables
just like the ASM tests.
2023-09-24 18:50:01 -07:00
Ryan Houdek f65b40f298 InstCountCI: Fail if inst count has changed 2023-09-24 17:14:08 -07:00
Ryan Houdek 5896c30954 CodeSizeValidation: Adds SPDX identifier 2023-09-18 21:30:30 -07:00
Ryan Houdek 6c2f8ab085 InstCountCI: Add log before compiling instruction
If CI faults out due to a bug then we would have no log as to which
instruction caused the issue.

I find myself adding this each time an assert fires to see what
instruction it was working on. Just add it directly.
2023-09-13 14:33:33 -07:00
Ryan Houdek 81a32c3998 FEXCore: Allows disabling telemetry at runtime
This is useful for InstCountCI so you can disable the telemetry
gathering even if enabled so it doesn't affect the CI system.
2023-08-30 12:59:41 -07:00
Ryan Houdek c5d147322f HostFeatures: Adds support for FCMA 2023-08-24 15:00:41 -07:00
Billy Laws bbfd15f801 LogMan: Commonise log level to string conversion 2023-08-18 04:36:31 -07:00
Ryan Houdek 8706f895d0 InstCountCI: Sanitize out vixl address calculations 2023-08-16 13:38:45 -07:00
Ryan Houdek 9753ebdebc InstCountCI: Support encoding expected Arm64 ASM in JSON
This will allow investigating the Arm64 directly next to the test, plus
publicly linking directly to badly behaving tests.

Perfect for nerdsniping implementations.
2023-08-16 01:50:06 -07:00
Mai df3d4efc80 Merge pull request #2904 from Sonicadvance1/instcountci_only_arm
GIthub: Only enable InstCountCI on an ARM platform
2023-08-15 17:33:10 -04:00
Ryan Houdek 1441cb76b9 HostFeatures: Adds support for overriding ARMv8.1 LSE atomics
Always enable it on the InstCountCI.
2023-08-15 14:12:27 -07:00
Ryan Houdek 04f1f073c8 InstCountCI: Adds RNG support
Some instructions in the SecondaryGroup need RNG support for testing.
2023-08-15 12:58:53 -07:00
Ryan Houdek a2c2b042b2 CodeSizeValidation: Fixes nullptr dereference 2023-08-14 16:04:20 -07:00
Ryan Houdek cbfea75037 Increase maximum instruction name to 128-bytes
Some long name instructions are going beyond 32-bytes. Obviously not
hurting to encode a few additional bytes.
2023-08-13 12:32:14 -07:00
Ryan Houdek e8e52af2e8 CodeSizeValidation: Adds support for overriding CLZero support
Vixl simulator by default doesn't support this.
2023-08-11 11:12:46 -07:00
Ryan Houdek acc7f2fa8f FEX: Adds instruction count CI
Implements CI for tracking instruction counts for generate blocks of
code when transforming from x86 to ARM64 assembly.

This will end up encompassing every instruction in our instruction
tables similarly to how our assembly tests try to test everything in our
instruction tables.

Incidentally, the data for this CI is generated using our assembly
tests. By enabling disassembly and instruction stats when executing a
suite of instructions, this gives the stats that can be added to a json
file.

The current implementation only implements the SecondGroup table of
instructions because it is a relatively small table and has known
inefficiencies in the instruction implementations. As this gets merged I
will be adding more tables of instructions to additional json files for
testing.

These JSON files will support adjusting CPU features regardless of the
host features so it can test implementations depending on different CPU
features. This will let us test things like one instruction having
different "optimal" implementations depending on if it supports SVE128,
SVE256, SVEI8MM, etc.

This initial instruction auditing is what found the bug in our vector
shift instructions by size of zero. If inspecting the result of the CI
run, you can tell that these instructions still aren't "optimal" because
they are doing loads and stores that can be eliminated.

The "Optimal" in the JSON is purely for human readable and grepping
ability to see what is optimal versus not. Same with the "Comment"
section.

According to my auditing spreadsheet, the total number of instructions
that will end up in these json files will be about 1000, but we will
likely end up with more since there will be edge cases that can be more
optimal depending on arguments.
2023-08-11 09:10:36 -07:00