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Code Issues Packages Projects Releases 67 Wiki Activity
13,021 Commits 11 Branches 71 Tags
530821fc4aa607ef2cd424d6dd2cdc2c2b9687ee
Commit Graph
2770 Commits
Author SHA1 Message Date
Lioncache 530821fc4a IR: Convert rounding modes to enum class 
Same behavior, but more compact
 2025-10-01 23:37:57 -04:00
Lioncache 863d1e0007 IR: Convert FenceType to an enum class 
Same thing minus an extra struct lingering around.
 2025-10-01 23:13:08 -04:00
Lioncache a798880ac8 IR: Convert CondClassType over to enum class 
Instead of having this sort of odd indirection through a struct type,
we can add support for defining custom enums in the IR description.

This lets us both get strong typing (and allow for weak typing, should
any enum in the future need it), without needing a struct for a basic
value type.

Even then, if we do need a struct for anything in the future, then
we still allow strong typing for values themselves while allowing
them to be used in various ways.
 2025-10-01 10:45:00 -04:00
Lioncache 84325d6b5c Arm64Emitter: Cull unnecessary includes 
Also fixes an indirect include.
 2025-09-30 09:32:25 -04:00
Lioncache 6b61093037 JITClass: Mark functions as static where applicable 
These don't depend on any class state.
 2025-09-29 23:42:43 -04:00
Ryan Houdek 7f8fffbb24 FEXCore: Implement support for AVX gathers with overflow 
Falls down the emulated path so we can zero extend the address
calculation. No way for SVE gathers to use 32-bit addressing.
 2025-09-29 16:06:02 -07:00
Ryan Houdek e5680e031d Merge pull request #4835 from pmatos/fix/classify 
Fix quiet and signalling nan propagation
 2025-09-23 11:17:37 -07:00
Paulo Matos e7a47a647c Fix quiet and signalling nan propagation 
This adds a new mode X87StrictReducedPrecision.
The strict reduced precision is like the reduced precision but adds extra checks,
like the currently implemented nan and snan propagations.

Fix for __builtin_issignaling() test of SPEC2017 classify test.
 2025-09-23 13:48:45 +02:00
Ryan Houdek c58db36a7c OpcodeDispatcher: Fixes telemetry on legacy segment read 2025-09-22 11:57:34 -07:00
LC 4593099882 Merge pull request #4896 from pmatos/fix/x87IsZero 
Remove unused IsZero; NFC
 2025-09-22 15:18:05 +02:00
Paulo Matos 21e29af48b Remove unused IsZero; NFC 2025-09-22 14:22:14 +02:00
Ryan Houdek efe401c7a4 OpcodeDispatcher: Fixes fxsave x87 register storing 
These get stored based on the current rotation of TOP. So we need to be
a bit careful with how we do this storing. A smidge of overhead, but
nothing unexpected.
 2025-09-19 14:04:32 -07:00
Ryan Houdek dd4f508b77 FEX: Fixes SIGILL reporting 
Two bug fixes here.
- We weren't reporting a correctl ErrorRegister. Needs to contain
  PF_INSTR at least.
- We weren't setting siginfo->si_addr in the case of `FaultToTopAndGeneratedException`

Fixes Mafia 2 (Classic)
 2025-09-18 11:26:15 -07:00
LC bdbeef3b9a Merge pull request #4884 from Sonicadvance1/fex_decodedinst_size 
Frontend: Improve DecodeInst size from 128 bytes to 80
 2025-09-16 10:05:33 +02:00
LC 8ead4a3c34 Merge pull request #4878 from Sonicadvance1/modrm_oob 
unittests/ASM: Implement modrm OOB tests
 2025-09-16 10:02:38 +02:00
LC 2d53a9b0dc Merge pull request #4885 from Sonicadvance1/remove_log_about_segments 
OpcodeDispatcher: Removes a log about unknown segments
 2025-09-16 10:01:27 +02:00
Lioncache 056abb5901 IR: Add missing includes 
Fixes some indirect includes while we're at it.
 2025-09-15 11:47:39 +02:00
Lioncache af28406dbc IR: Remove unnecessary friend class declarations from OrderedNode 
These classes don't exist anymore, so we can get rid of these declarations.
 2025-09-15 11:37:37 +02:00
Ryan Houdek a30593efd6 OpcodeDispatcher: Removes a log about unknown segments 
This behaves like `UnimplementedOp`, giving a SIGILL if it actually gets
hit.
 2025-09-12 17:34:16 -07:00
Ryan Houdek 3fa400bc55 Frontend: Improve DecodeInst size from 128 bytes to 80 
We were paying a large cost per Literal type that we can special case
for the two class of instructions that use a 64-bit literal.

If we packed this would get to a further 62 bytes but probably not worth
it.
 2025-09-12 16:07:01 -07:00
Ryan Houdek 90ea16325a Frontend: Move a couple of members from DecodeInst 
LastEscapePrefix doesn't need to be in DecodeInst, and we can have a
couple of flags for ForceTSO/DecodedSIB/DecodedModRM.
 2025-09-12 15:37:18 -07:00
Ryan Houdek d6a466ac0b OpcodeDispatcher: Fixes 16-bit movbe to memory 2025-09-12 12:42:18 -07:00
Ryan Houdek 7273041314 FEXInterpreter: Remove FEXLoader 
Doesn't /quite/ remove the ArgumentLoader because it is intertwined with
LinuxEmulation in an annoying way that will take another step to remove.
 2025-09-12 10:24:58 -07:00
Lioncache e0f27bb855 Interface/Context: Remove unnecessary headers/forward declarations 2025-09-12 04:13:26 -04:00
Ryan Houdek 74b59f458d OpcodeDispatcher: Fix misaligned clang-format 2025-09-11 14:27:43 -07:00
Ryan Houdek 61719115e5 Merge pull request #4817 from neobrain/refactor_code_cache_new_interfaces 
CodeCache: Introduce new interfaces
 2025-09-11 12:59:33 -07:00
Ryan Houdek 0eedd55dfd Merge pull request #4866 from neobrain/refactor_reformat 
Update code formatting
 2025-09-11 10:13:42 -07:00
Ryan Houdek 4a9170e981 Merge pull request #4837 from bylaws/x87opt 
X87: Better cache intermediate results in the X87 slowpath
 2025-09-11 10:12:36 -07:00
Tony Wasserka b5b8ff01d5 CodeCache: Move LibraryJITNaming and GDBSymbols checks to Core 2025-09-11 17:03:50 +02:00
Tony Wasserka 6c86ffdeb7 Core: Remove redundant nullptr check 2025-09-11 17:03:50 +02:00
Tony Wasserka 70a1d92d9f CodeCache: Drop ComputeCodeMapId member function 2025-09-11 17:03:50 +02:00
Tony Wasserka 0749477eb9 CodeCache: Introduce revamped interfaces 2025-09-11 17:03:50 +02:00
Tony Wasserka db601d333b Core: Rename and move AOTIR.cpp and AOTIR.h 
The new names better reflect the contents after recent/upcoming API changes.
 2025-09-11 10:49:07 +02:00
Tony Wasserka af1c2cccac Rename AOTIR.cpp to CodeCache.cpp 2025-09-11 10:49:07 +02:00
Tony Wasserka 9fdd96af61 Update code formatting 2025-09-11 10:40:29 +02:00
LC 30dd9ed267 Merge pull request #4863 from Sonicadvance1/more_cpuid 
CPUID: Adds new CPU product names that exist
 2025-09-10 23:09:33 -04:00
Ryan Houdek 58b5620f97 FEXCore: Fixes OOB access on x87 reduced precision loads 
x87 80-bit loads, both BCD and regular tword were loading 128-bits of
data when reduced precision was enabled. This was an oversight from the
previous fix a while ago.

Adds a specific reduced precision test for this, and updates the current
test to ensure stores are still tested as well.
 2025-09-10 19:19:55 -07:00
Ryan Houdek 327b62ea45 CPUID: Adds new CPU product names that exist 2025-09-10 11:51:04 -07:00
Ryan Houdek 91c6d693df Merge pull request #4860 from bylaws/susprip 
JIT: Check for suspend interrupts at back-edges
 2025-09-10 10:29:37 -07:00
Lioncache ad3a024b69 IREmitter: Remove friend class declarations 
These no longer need specific access to internals.
 2025-09-10 13:12:58 -04:00
Tony Wasserka fee9e91c4f Core: Drop support for TSO auto migration 2025-09-10 15:36:23 +02:00
Tony Wasserka 1dc560d45a InstCountCI: Explicitly disable TSO by default 2025-09-10 15:36:23 +02:00
Billy Laws 93096c27f9 Dispatcher: Fix FABI_F32_I16_F80_PTR argument size 
This takes an f80 as input and returns an f32. A copy-paste error had
this truncating the input float if !TMP_ABIARGS.
 2025-09-10 03:14:30 +01:00
Billy Laws d2714f3338 JIT: Check for suspend interrupts at back-edges 
Avoids most cases where an infinite loop could lead to suspend interrups
never getting checked.
 2025-09-09 22:35:52 +01:00
Billy Laws b917db34c7 OpcodeDispatcher: Emit RIP metadata for RIP-setting instructions 2025-09-09 22:35:52 +01:00
Billy Laws a2286cb00a OpDispatcher: Only use the MM register cache when in MMX state 
Since the X87 pass now performs its own MM register caching, these must
be mutually exclusive.
 2025-09-09 21:30:33 +01:00
Billy Laws 481787d45c OpDispatcher: Avoid using the register cache for AbridgedFTW 
This is now cached internally in the X87 pass, and all operations
outside of that that use it are rare so can afford loading/storing
directly from context after flushing x87 regs.
 2025-09-09 21:30:30 +01:00
Billy Laws 6789919fca X87StackOptimization: Don't flush to mem when entering slow path 2025-09-09 21:29:12 +01:00
Billy Laws d8c615ec65 OpcodeDispatcher: Only flush MMX registers on MMX -> x87 transitions 
Flushing other regs is not necessary, and breaks any ConvertNZCVToX87 use
which relies previously saved NZCV values as the flag-setting NZCV op after
the save could trigger a flush of NZCV.
 2025-09-09 21:29:12 +01:00
Billy Laws 6a1eb0e508 X87StackOptimization: Defer FTW valid bits calculation 2025-09-09 21:29:12 +01:00